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Added coprocessor registers, and support for 6 operands(MCR/MRC instructions, etc)

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git-svn-id: branches/laksen/arm-embedded@22778 -
This commit is contained in:
Jeppe Johansen 2012-10-19 18:23:14 +00:00
parent 9892aea2ca
commit 666332385d
18 changed files with 169 additions and 18 deletions
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1
compiler/arm/armatt.inc
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@ -50,6 +50,7 @@
'mcr',
'mla',
'mov',
'mrc',
'mrs',
'msr',
'mnf',

1
compiler/arm/armatts.inc
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@ -326,5 +326,6 @@ attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE,
attsufNONE
);

4
compiler/arm/armins.dat
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@ -235,7 +235,7 @@ reg32,imm8,fpureg \xF0\x02\x01 FPA
[LOGcc]
[MCR]
reg32,mem32 \320\301\1\x13\110 ARM7
; reg32,mem32 \320\301\1\x13\110 ARM7
[MLAcc]
reg32,reg32,reg32,reg32 \x15\x00\x20\x90 ARM7
@ -247,7 +247,7 @@ reg32,reg32,reg32,reg32 \x15\x00\x20\x90 ARM7
; reg32,reg32,imm \xA\x1\xA0 ARM7
; reg32,imm \xB\x3\xA0 ARM7
; [MRC]
[MRC]
; reg32,reg32 \321\301\1\x13\110 ARM7
[MRScc]

2
compiler/arm/armnop.inc
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@ -1,2 +1,2 @@
{ don't edit, this file is generated from armins.dat }
106;
105;

1
compiler/arm/armop.inc
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@ -50,6 +50,7 @@ A_LOG,
A_MCR,
A_MLA,
A_MOV,
A_MRC,
A_MRS,
A_MSR,
A_MNF,

21
compiler/arm/armreg.dat
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@ -110,4 +110,23 @@ D31,$04,$07,$1F,d31,0,0
CPSR,$05,$00,$00,cpsr,0,0
FPSCR,$05,$00,$01,fpscr,0,0
SPSR,$05,$00,$02,spsr,0,0
APSR_nzcv,$05,$00,$03,apsr_nzcv,0,0
APSR_nzcv,$05,$00,$03,apsr_nzcv,0,0
; coprocessor registers
CR0,$05,$00,$04,cr0,0,0
CR1,$05,$00,$05,cr1,0,0
CR2,$05,$00,$06,cr2,0,0
CR3,$05,$00,$07,cr3,0,0
CR4,$05,$00,$08,cr4,0,0
CR5,$05,$00,$09,cr5,0,0
CR6,$05,$00,$0A,cr6,0,0
CR7,$05,$00,$0B,cr7,0,0
CR8,$05,$00,$0C,cr8,0,0
CR9,$05,$00,$0D,cr9,0,0
CR10,$05,$00,$0E,cr10,0,0
CR11,$05,$00,$0F,cr11,0,0
CR12,$05,$00,$10,cr12,0,0
CR13,$05,$00,$11,cr13,0,0
CR14,$05,$00,$12,cr14,0,0
CR15,$05,$00,$13,cr15,0,0
; coprocessors
p15,$05,$00,$14,p15,0,0

7
compiler/arm/armtab.inc
View File

@ -385,13 +385,6 @@
code : #240#2#1;
flags : if_fpa
),
(
opcode : A_MCR;
ops : 2;
optypes : (ot_reg32,ot_memory or ot_bits32,ot_none,ot_none);
code : #208#193#1#19#72;
flags : if_arm7
),
(
opcode : A_MLA;
ops : 4;

4
compiler/arm/cpubase.pas
View File

@ -48,7 +48,7 @@ unit cpubase;
TAsmOp= {$i armop.inc}
{This is a bit of a hack, because there are more than 256 ARM Assembly Ops
But FPC currently can't handle more than 256 elements in a set.}
TCommonAsmOps = Set of A_None .. A_UQSAX;
TCommonAsmOps = Set of A_None .. A_UQASX;
{ This should define the array of instructions as string }
op2strtable=array[tasmop] of string[11];
@ -230,7 +230,7 @@ unit cpubase;
*****************************************************************************}
const
max_operands = 4;
max_operands = 6;
maxintregs = 15;
maxfpuregs = 8;

2
compiler/arm/raarmgas.pas
View File

@ -1061,7 +1061,7 @@ Unit raarmgas;
AS_COMMA: { Operand delimiter }
Begin
if ((instr.opcode in [A_MOV, A_MVN, A_CMP, A_CMN, A_TST, A_TEQ]) and (operandnum=2)) or
((operandnum=3) and not(instr.opcode in [A_UMLAL,A_UMULL,A_SMLAL,A_SMULL,A_MLA])) then
((operandnum=3) and not(instr.opcode in [A_UMLAL,A_UMULL,A_SMLAL,A_SMULL,A_MLA,A_MRC,A_MCR,A_MCRR,A_MRRC])) then
begin
Consume(AS_COMMA);
if not(TryBuildShifterOp(instr.Operands[operandnum+1] as tarmoperand)) then

17
compiler/arm/rarmcon.inc
View File

@ -92,3 +92,20 @@ NR_CPSR = tregister($05000000);
NR_FPSCR = tregister($05000001);
NR_SPSR = tregister($05000002);
NR_APSR_nzcv = tregister($05000003);
NR_CR0 = tregister($05000004);
NR_CR1 = tregister($05000005);
NR_CR2 = tregister($05000006);
NR_CR3 = tregister($05000007);
NR_CR4 = tregister($05000008);
NR_CR5 = tregister($05000009);
NR_CR6 = tregister($0500000A);
NR_CR7 = tregister($0500000B);
NR_CR8 = tregister($0500000C);
NR_CR9 = tregister($0500000D);
NR_CR10 = tregister($0500000E);
NR_CR11 = tregister($0500000F);
NR_CR12 = tregister($05000010);
NR_CR13 = tregister($05000011);
NR_CR14 = tregister($05000012);
NR_CR15 = tregister($05000013);
NR_p15 = tregister($05000014);

17
compiler/arm/rarmdwa.inc
View File

@ -91,4 +91,21 @@
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0

2
compiler/arm/rarmnor.inc
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@ -1,2 +1,2 @@
{ don't edit, this file is generated from armreg.dat }
93
110

19
compiler/arm/rarmnum.inc
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@ -91,4 +91,21 @@ tregister($0407001F),
tregister($05000000),
tregister($05000001),
tregister($05000002),
tregister($05000003)
tregister($05000003),
tregister($05000004),
tregister($05000005),
tregister($05000006),
tregister($05000007),
tregister($05000008),
tregister($05000009),
tregister($0500000A),
tregister($0500000B),
tregister($0500000C),
tregister($0500000D),
tregister($0500000E),
tregister($0500000F),
tregister($05000010),
tregister($05000011),
tregister($05000012),
tregister($05000013),
tregister($05000014)

19
compiler/arm/rarmrni.inc
View File

@ -91,4 +91,21 @@
89,
90,
91,
92
92,
93,
94,
95,
96,
97,
98,
99,
100,
101,
102,
103,
104,
105,
106,
107,
108,
109

17
compiler/arm/rarmsri.inc
View File

@ -2,6 +2,22 @@
0,
92,
89,
93,
94,
103,
104,
105,
106,
107,
108,
95,
96,
97,
98,
99,
100,
101,
102,
27,
30,
57,
@ -43,6 +59,7 @@
23,
24,
90,
109,
1,
2,
11,

17
compiler/arm/rarmsta.inc
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@ -91,4 +91,21 @@
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0

19
compiler/arm/rarmstd.inc
View File

@ -91,4 +91,21 @@
'cpsr',
'fpscr',
'spsr',
'apsr_nzcv'
'apsr_nzcv',
'cr0',
'cr1',
'cr2',
'cr3',
'cr4',
'cr5',
'cr6',
'cr7',
'cr8',
'cr9',
'cr10',
'cr11',
'cr12',
'cr13',
'cr14',
'cr15',
'p15'

17
compiler/arm/rarmsup.inc
View File

@ -92,3 +92,20 @@ RS_CPSR = $00;
RS_FPSCR = $01;
RS_SPSR = $02;
RS_APSR_nzcv = $03;
RS_CR0 = $04;
RS_CR1 = $05;
RS_CR2 = $06;
RS_CR3 = $07;
RS_CR4 = $08;
RS_CR5 = $09;
RS_CR6 = $0A;
RS_CR7 = $0B;
RS_CR8 = $0C;
RS_CR9 = $0D;
RS_CR10 = $0E;
RS_CR11 = $0F;
RS_CR12 = $10;
RS_CR13 = $11;
RS_CR14 = $12;
RS_CR15 = $13;
RS_p15 = $14;