From 670c61e7609d02e978a6b0b7f26effdc132a1840 Mon Sep 17 00:00:00 2001 From: florian Date: Sun, 26 Jan 2020 14:35:26 +0000 Subject: [PATCH] * patch by Christo Crause: support for megaAVR 0 and tinyAVR 0/1, #36616, part 1/3 git-svn-id: trunk@44036 - --- compiler/avr/aoptcpu.pas | 28 +++++++-- compiler/avr/cgcpu.pas | 42 +++++++------- compiler/avr/cpuinfo.pas | 107 +++++++++++++++++++++++++++++------ compiler/systems/t_embed.pas | 2 + 4 files changed, 138 insertions(+), 41 deletions(-) diff --git a/compiler/avr/aoptcpu.pas b/compiler/avr/aoptcpu.pas index 15b7353365..c8b999808c 100644 --- a/compiler/avr/aoptcpu.pas +++ b/compiler/avr/aoptcpu.pas @@ -433,13 +433,21 @@ Implementation (getsupreg(taicpu(p).oper[0]^.ref^.base)=RS_NO) and (getsupreg(taicpu(p).oper[0]^.ref^.index)=RS_NO) and (taicpu(p).oper[0]^.ref^.addressmode=AM_UNCHANGED) and - (taicpu(p).oper[0]^.ref^.offset>=32) and - (taicpu(p).oper[0]^.ref^.offset<=95) then + // avrxmega3 doesn't map registers into data space so no offset to subtract + (((current_settings.cputype = cpu_avrxmega3) and + (taicpu(p).oper[0]^.ref^.offset>=0) and + (taicpu(p).oper[0]^.ref^.offset<=63)) or + ((current_settings.cputype <> cpu_avrxmega3) and + (taicpu(p).oper[0]^.ref^.offset>=32) and + (taicpu(p).oper[0]^.ref^.offset<=95))) then begin DebugMsg('Peephole Sts2Out performed', p); taicpu(p).opcode:=A_OUT; - taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset-32); + if current_settings.cputype = cpu_avrxmega3 then + taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset) + else + taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset-32); end; A_LDS: if (taicpu(p).oper[1]^.ref^.symbol=nil) and @@ -447,13 +455,21 @@ Implementation (getsupreg(taicpu(p).oper[1]^.ref^.base)=RS_NO) and (getsupreg(taicpu(p).oper[1]^.ref^.index)=RS_NO) and (taicpu(p).oper[1]^.ref^.addressmode=AM_UNCHANGED) and - (taicpu(p).oper[1]^.ref^.offset>=32) and - (taicpu(p).oper[1]^.ref^.offset<=95) then + // avrxmega3 doesn't map registers into data space so no offset to subtract + (((current_settings.cputype = cpu_avrxmega3) and + (taicpu(p).oper[1]^.ref^.offset>=0) and + (taicpu(p).oper[1]^.ref^.offset<=63)) or + ((current_settings.cputype <> cpu_avrxmega3) and + (taicpu(p).oper[1]^.ref^.offset>=32) and + (taicpu(p).oper[1]^.ref^.offset<=95))) then begin DebugMsg('Peephole Lds2In performed', p); taicpu(p).opcode:=A_IN; - taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset-32); + if current_settings.cputype = cpu_avrxmega3 then + taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset) + else + taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset-32); end; A_IN: if GetNextInstruction(p,hp1) then diff --git a/compiler/avr/cgcpu.pas b/compiler/avr/cgcpu.pas index ec39ff66f9..fc8094fc96 100644 --- a/compiler/avr/cgcpu.pas +++ b/compiler/avr/cgcpu.pas @@ -1375,8 +1375,11 @@ unit cgcpu; // Write to 16 bit ioreg, first high byte then low byte // sequence required for 16 bit timer registers // See e.g. atmega328p manual para 15.3 Accessing 16 bit registers - if (fromsize in [OS_16, OS_S16]) and QuickRef and (href.offset > 31) - and (href.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then + // Avrxmega3: write low byte first then high byte + // See e.g. megaAVR-0 family data sheet 7.5.6 Accessing 16-bit registers + if (current_settings.cputype <> cpu_avrxmega3) and + (fromsize in [OS_16, OS_S16]) and QuickRef and (href.offset > 31) and + (href.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then begin tmpreg:=GetNextReg(reg); href.addressmode:=AM_UNCHANGED; @@ -2592,23 +2595,24 @@ unit cgcpu; dstref:=dest; end; - // CC - // If dest is an ioreg (31 < offset < srambase) and size = 16 bit then - // load high byte first, then low byte - if (len = 2) and DestQuickRef - and (dest.offset > 31) - and (dest.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then - begin - // If src is also a 16 bit ioreg then read low byte then high byte - if SrcQuickRef and (srcref.offset > 31) - and (srcref.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then - begin - // First read source into temp registers - tmpreg:=getintregister(list, OS_16); - list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref)); - inc(srcref.offset); - tmpreg2:=GetNextReg(tmpreg); - list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg2,srcref)); + // CC + // If dest is an ioreg (31 < offset < srambase) and size = 16 bit then + // write high byte first, then low byte + // but not for avrxmega3 + if (len = 2) and DestQuickRef and (current_settings.cputype <> cpu_avrxmega3) and + (dest.offset > 31) and + (dest.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then + begin + // If src is also a 16 bit ioreg then read low byte then high byte + if SrcQuickRef and (srcref.offset > 31) + and (srcref.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then + begin + // First read source into temp registers + tmpreg:=getintregister(list, OS_16); + list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref)); + inc(srcref.offset); + tmpreg2:=GetNextReg(tmpreg); + list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg2,srcref)); // then move temp registers to dest in reverse order inc(dstref.offset); diff --git a/compiler/avr/cpuinfo.pas b/compiler/avr/cpuinfo.pas index a7648ac6b9..9746ef1adb 100644 --- a/compiler/avr/cpuinfo.pas +++ b/compiler/avr/cpuinfo.pas @@ -47,7 +47,8 @@ Type cpu_avr4, cpu_avr5, cpu_avr51, - cpu_avr6 + cpu_avr6, + cpu_avrxmega3 ); tfputype = @@ -204,7 +205,42 @@ Type ct_atmega325, ct_atmega169pa, ct_attiny261a, - ct_attiny25 + ct_attiny25, + ct_atmega808, + ct_atmega809, + ct_atmega1608, + ct_atmega1609, + ct_atmega3208, + ct_atmega3209, + ct_atmega4808, + ct_atmega4809, + ct_attiny202, + ct_attiny204, + ct_attiny212, + ct_attiny214, + ct_attiny402, + ct_attiny404, + ct_attiny406, + ct_attiny412, + ct_attiny414, + ct_attiny416, + ct_attiny416auto, + ct_attiny417, + ct_attiny804, + ct_attiny806, + ct_attiny807, + ct_attiny814, + ct_attiny816, + ct_attiny817, + ct_attiny1604, + ct_attiny1606, + ct_attiny1607, + ct_attiny1614, + ct_attiny1616, + ct_attiny1617, + ct_attiny3214, + ct_attiny3216, + ct_attiny3217 ); tcontrollerdatatype = record @@ -235,7 +271,7 @@ Const pocall_softfloat ]; - cputypestr : array[tcputype] of string[8] = ('', + cputypestr : array[tcputype] of string[9] = ('', 'AVRTINY', 'AVR1', 'AVR2', @@ -246,7 +282,8 @@ Const 'AVR4', 'AVR5', 'AVR51', - 'AVR6' + 'AVR6', + 'AVRXMEGA3' ); fputypestr : array[tfputype] of string[6] = ( @@ -428,6 +465,43 @@ Const ,(controllertypestr:'ATMEGA169PA'; controllerunitstr:'ATMEGA169PA'; cputype: cpu_avr5; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:256; sramsize:1024; eeprombase:0; eepromsize:512) ,(controllertypestr:'ATTINY261A'; controllerunitstr:'ATTINY261A'; cputype: cpu_avr25; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:96; sramsize:128; eeprombase:0; eepromsize:128) ,(controllertypestr:'ATTINY25'; controllerunitstr:'ATTINY25'; cputype: cpu_avr25; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:96; sramsize:128; eeprombase:0; eepromsize:128) + // megaAVR0 series + ,(controllertypestr:'ATMEGA808'; controllerunitstr:'ATMEGA808'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATMEGA809'; controllerunitstr:'ATMEGA809'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATMEGA1608'; controllerunitstr:'ATMEGA1608'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATMEGA1609'; controllerunitstr:'ATMEGA1609'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATMEGA3208'; controllerunitstr:'ATMEGA3208'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:12288; sramsize:4096; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATMEGA3209'; controllerunitstr:'ATMEGA3209'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:12288; sramsize:4096; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATMEGA4808'; controllerunitstr:'ATMEGA4808'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:49152; srambase:10240; sramsize:6144; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATMEGA4809'; controllerunitstr:'ATMEGA4809'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:49152; srambase:10240; sramsize:6144; eeprombase:5120; eepromsize:256) + // tinyAVR 0/1 series + ,(controllertypestr:'ATTINY202'; controllerunitstr:'ATTINY202'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:16256; sramsize:128; eeprombase:5120; eepromsize:64) + ,(controllertypestr:'ATTINY204'; controllerunitstr:'ATTINY204'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:16256; sramsize:128; eeprombase:5120; eepromsize:64) + ,(controllertypestr:'ATTINY212'; controllerunitstr:'ATTINY212'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:16256; sramsize:128; eeprombase:5120; eepromsize:64) + ,(controllertypestr:'ATTINY214'; controllerunitstr:'ATTINY214'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:16256; sramsize:128; eeprombase:5120; eepromsize:64) + ,(controllertypestr:'ATTINY402'; controllerunitstr:'ATTINY402'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY404'; controllerunitstr:'ATTINY404'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY406'; controllerunitstr:'ATTINY406'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY412'; controllerunitstr:'ATTINY412'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY414'; controllerunitstr:'ATTINY414'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY416'; controllerunitstr:'ATTINY416'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY416AUTO'; controllerunitstr:'ATTINY416AUTO'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY417'; controllerunitstr:'ATTINY417'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY804'; controllerunitstr:'ATTINY804'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY806'; controllerunitstr:'ATTINY806'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY807'; controllerunitstr:'ATTINY807'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY814'; controllerunitstr:'ATTINY814'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY816'; controllerunitstr:'ATTINY816'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY817'; controllerunitstr:'ATTINY817'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128) + ,(controllertypestr:'ATTINY1604'; controllerunitstr:'ATTINY1604'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATTINY1606'; controllerunitstr:'ATTINY1606'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATTINY1607'; controllerunitstr:'ATTINY1607'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATTINY1614'; controllerunitstr:'ATTINY1614'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATTINY1616'; controllerunitstr:'ATTINY1616'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATTINY1617'; controllerunitstr:'ATTINY1617'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATTINY3214'; controllerunitstr:'ATTINY3214'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATTINY3216'; controllerunitstr:'ATTINY3216'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256) + ,(controllertypestr:'ATTINY3217'; controllerunitstr:'ATTINY3217'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256) ); { Supported optimizations, only used for information } @@ -461,18 +535,19 @@ Const const cpu_capabilities : array[tcputype] of set of tcpuflags = - ( { cpu_none } [], - { cpu_avrtiny } [CPUAVR_16_REGS,CPUAVR_2_BYTE_PC], - { cpu_avr1 } [CPUAVR_2_BYTE_PC], - { cpu_avr2 } [CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC], - { cpu_avr25 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC], - { cpu_avr3 } [CPUAVR_HAS_JMP_CALL,CPUAVR_2_BYTE_PC], - { cpu_avr31 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_2_BYTE_PC], - { cpu_avr35 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC], - { cpu_avr4 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC], - { cpu_avr5 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC], - { cpu_avr51 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_2_BYTE_PC], - { cpu_avr6 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_3_BYTE_PC] + ( { cpu_none } [], + { cpu_avrtiny } [CPUAVR_16_REGS,CPUAVR_2_BYTE_PC], + { cpu_avr1 } [CPUAVR_2_BYTE_PC], + { cpu_avr2 } [CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC], + { cpu_avr25 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC], + { cpu_avr3 } [CPUAVR_HAS_JMP_CALL,CPUAVR_2_BYTE_PC], + { cpu_avr31 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_2_BYTE_PC], + { cpu_avr35 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC], + { cpu_avr4 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC], + { cpu_avr5 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC], + { cpu_avr51 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_2_BYTE_PC], + { cpu_avr6 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_3_BYTE_PC], + { cpu_avrxmega3 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC] ); Implementation diff --git a/compiler/systems/t_embed.pas b/compiler/systems/t_embed.pas index f844c5321a..3d59274615 100644 --- a/compiler/systems/t_embed.pas +++ b/compiler/systems/t_embed.pas @@ -824,6 +824,8 @@ begin Add('OUTPUT_ARCH(avr:51)'); cpu_avr6: Add('OUTPUT_ARCH(avr:6)'); + cpu_avrxmega3: + Add('OUTPUT_ARCH(avr:103)'); else Internalerror(2015072701); end;