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https://gitlab.com/freepascal.org/fpc/source.git
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* x86: New SHR-based optimisations
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
e21186cac0
commit
6757bf3832
@ -191,6 +191,8 @@ unit aoptcpu;
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end;
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A_SHL, A_SAL:
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Result:=OptPass1SHLSAL(p);
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A_SHR:
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Result:=OptPass1SHR(p);
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A_SUB:
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Result:=OptPass1Sub(p);
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A_Jcc:
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@ -135,6 +135,7 @@ unit aoptx86;
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class function IsExitCode(p : tai) : boolean; static;
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class function isFoldableArithOp(hp1 : taicpu; reg : tregister) : boolean; static;
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class function IsShrMovZFoldable(shr_size, movz_size: topsize; Shift: TCGInt): Boolean; static;
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procedure RemoveLastDeallocForFuncRes(p : tai);
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function DoSubAddOpt(var p : tai) : Boolean;
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@ -157,6 +158,7 @@ unit aoptx86;
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function OptPass1LEA(var p : tai) : boolean;
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function OptPass1Sub(var p : tai) : boolean;
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function OptPass1SHLSAL(var p : tai) : boolean;
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function OptPass1SHR(var p : tai) : boolean;
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function OptPass1FSTP(var p : tai) : boolean;
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function OptPass1FLD(var p : tai) : boolean;
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function OptPass1Cmp(var p : tai) : boolean;
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@ -6448,6 +6450,146 @@ unit aoptx86;
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end;
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class function TX86AsmOptimizer.IsShrMovZFoldable(shr_size, movz_size: topsize; Shift: TCGInt): Boolean;
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begin
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case shr_size of
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S_B:
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{ No valid combinations }
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Result := False;
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S_W:
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Result := (Shift >= 8) and (movz_size = S_BW);
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S_L:
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Result :=
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(Shift >= 24) { Any opsize is valid for this shift } or
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((Shift >= 16) and (movz_size = S_WL));
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{$ifdef x86_64}
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S_Q:
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Result :=
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(Shift >= 56) { Any opsize is valid for this shift } or
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((Shift >= 48) and (movz_size = S_WL));
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{$endif x86_64}
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else
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InternalError(2022081510);
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end;
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end;
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function TX86AsmOptimizer.OptPass1SHR(var p : tai) : boolean;
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var
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hp1, hp2: tai;
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Shift: TCGInt;
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LimitSize: Topsize;
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DoNotMerge: Boolean;
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begin
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Result := False;
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{ All these optimisations work on "shr const,%reg" }
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if not MatchOpType(taicpu(p), top_const, top_reg) then
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Exit;
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DoNotMerge := False;
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Shift := taicpu(p).oper[0]^.val;
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LimitSize := taicpu(p).opsize;
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hp1 := p;
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repeat
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if not GetNextInstructionUsingReg(hp1, hp1, taicpu(p).oper[1]^.reg) or (hp1.typ <> ait_instruction) then
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Exit;
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case taicpu(hp1).opcode of
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A_TEST, A_CMP, A_Jcc:
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{ Skip over conditional jumps and relevant comparisons }
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Continue;
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A_MOVZX:
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if MatchOpType(taicpu(hp1), top_reg, top_reg) and
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SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(p).oper[1]^.reg) then
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begin
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{ Since the original register is being read as is, subsequent
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SHRs must not be merged at this point }
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DoNotMerge := True;
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if IsShrMovZFoldable(taicpu(p).opsize, taicpu(hp1).opsize, Shift) then
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begin
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if not SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then { Different register target }
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begin
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DebugMsg(SPeepholeOptimization + 'Converted MOVZX instruction to MOV since previous SHR makes zero-extension unnecessary (ShrMovz2ShrMov 1)', hp1);
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taicpu(hp1).opcode := A_MOV;
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setsubreg(taicpu(hp1).oper[0]^.reg, getsubreg(taicpu(hp1).oper[1]^.reg));
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case taicpu(hp1).opsize of
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S_BW:
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taicpu(hp1).opsize := S_W;
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S_BL, S_WL:
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taicpu(hp1).opsize := S_L;
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else
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InternalError(2022081503);
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end;
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{ p itself hasn't changed, so no need to set Result to True }
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Include(OptsToCheck, aoc_ForceNewIteration);
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{ See if there's anything afterwards that can be
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optimised, since the input register hasn't changed }
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Continue;
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end;
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{ NOTE: If the MOVZX instruction reads and writes the same
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register, defer this to the post-peephole optimisation stage }
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Exit;
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end;
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end;
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A_SHL, A_SAL, A_SHR:
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if (taicpu(hp1).opsize <= LimitSize) and
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MatchOpType(taicpu(hp1), top_const, top_reg) and
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SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, taicpu(p).oper[1]^.reg) then
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begin
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{ Make sure the sizes don't exceed the register size limit
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(measured by the shift value falling below the limit) }
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if taicpu(hp1).opsize < LimitSize then
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LimitSize := taicpu(hp1).opsize;
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if taicpu(hp1).opcode = A_SHR then
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Inc(Shift, taicpu(hp1).oper[0]^.val)
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else
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begin
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Dec(Shift, taicpu(hp1).oper[0]^.val);
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DoNotMerge := True;
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end;
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if Shift < topsize2memsize[taicpu(p).opsize] - topsize2memsize[LimitSize] then
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Exit;
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{ Since we've established that the combined shift is within
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limits, we can actually combine the adjacent SHR
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instructions even if they're different sizes }
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if not DoNotMerge and (taicpu(hp1).opcode = A_SHR) then
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begin
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hp2 := tai(hp1.Previous);
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DebugMsg(SPeepholeOptimization + 'ShrShr2Shr 1', p);
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Inc(taicpu(p).oper[0]^.val, taicpu(hp1).oper[0]^.val);
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RemoveInstruction(hp1);
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hp1 := hp2;
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{ Though p has changed, only the constant has, and its
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effects can still be detected on the next iteration of
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the repeat..until loop }
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Include(OptsToCheck, aoc_ForceNewIteration);
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end;
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{ Move onto the next instruction }
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Continue;
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end;
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else
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;
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end;
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Break;
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until False;
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end;
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function TX86AsmOptimizer.CheckMemoryWrite(var first_mov, second_mov: taicpu): Boolean;
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var
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CurrentRef: TReference;
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@ -12930,36 +13072,193 @@ unit aoptx86;
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function TX86AsmOptimizer.PostPeepholeOptShr(var p : tai) : boolean;
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var
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hp1: tai;
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hp1, hp2: tai;
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IdentityMask, Shift: TCGInt;
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LimitSize: Topsize;
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DoNotMerge: Boolean;
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begin
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{ Detect:
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shr x, %ax (x > 0)
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...
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movzwl %ax,%eax
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Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
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}
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Result := False;
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if MatchOpType(taicpu(p), top_const, top_reg) and
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(taicpu(p).oper[1]^.reg = NR_AX) and { This is also enough to determine that opsize = S_W }
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(taicpu(p).oper[0]^.val > 0) and
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GetNextInstructionUsingReg(p, hp1, NR_EAX) and
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MatchInstruction(hp1, A_MOVZX, [S_WL]) and
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MatchOperand(taicpu(hp1).oper[0]^, NR_AX) and
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MatchOperand(taicpu(hp1).oper[1]^, NR_EAX) then
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begin
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DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via ShrMovz2ShrCwtl)', hp1);
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taicpu(hp1).opcode := A_CWDE;
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taicpu(hp1).clearop(0);
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taicpu(hp1).clearop(1);
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taicpu(hp1).ops := 0;
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{ A change was made, but not with p, so move forward 1 }
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p := tai(p.Next);
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Result := True;
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{ All these optimisations work on "shr const,%reg" }
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if not MatchOpType(taicpu(p), top_const, top_reg) then
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Exit;
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DoNotMerge := False;
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Shift := taicpu(p).oper[0]^.val;
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LimitSize := taicpu(p).opsize;
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hp1 := p;
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repeat
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if not GetNextInstructionUsingReg(hp1, hp1, taicpu(p).oper[1]^.reg) or (hp1.typ <> ait_instruction) then
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Exit;
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{ Detect:
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shr x, %reg
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and y, %reg
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If and y, %reg doesn't actually change the value of %reg (e.g. with
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"shrl $24,%reg; andl $255,%reg", remove the AND instruction.
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}
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case taicpu(hp1).opcode of
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A_AND:
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if (taicpu(hp1).opsize = taicpu(p).opsize) and
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MatchOpType(taicpu(hp1), top_const, top_reg) and
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(taicpu(hp1).oper[1]^.reg = taicpu(p).oper[1]^.reg) then
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begin
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{ Make sure the FLAGS register isn't in use }
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TransferUsedRegs(TmpUsedRegs);
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hp2 := p;
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repeat
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UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
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until not GetNextInstruction(hp2, hp2) or (hp2 = hp1);
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if not RegUsedAfterInstruction(NR_DEFAULTFLAGS, hp1, TmpUsedRegs) then
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begin
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{ Generate the identity mask }
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case taicpu(p).opsize of
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S_B:
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IdentityMask := $FF shr Shift;
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S_W:
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IdentityMask := $FFFF shr Shift;
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S_L:
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IdentityMask := $FFFFFFFF shr Shift;
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{$ifdef x86_64}
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S_Q:
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{ We need to force the operands to be unsigned 64-bit
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integers otherwise the wrong value is generated }
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IdentityMask := TCGInt(QWord($FFFFFFFFFFFFFFFF) shr QWord(Shift));
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{$endif x86_64}
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else
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InternalError(2022081501);
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end;
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if (taicpu(hp1).oper[0]^.val and IdentityMask) = IdentityMask then
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begin
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DebugMsg(SPeepholeOptimization + 'Removed AND instruction since previous SHR makes this an identity operation (ShrAnd2Shr)', hp1);
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{ All the possible 1 bits are covered, so we can remove the AND }
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hp2 := tai(hp1.Previous);
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RemoveInstruction(hp1);
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{ p wasn't actually changed, so don't set Result to True,
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but a change was nonetheless made elsewhere }
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Include(OptsToCheck, aoc_ForceNewIteration);
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{ Do another pass in case other AND or MOVZX instructions
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follow }
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hp1 := hp2;
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Continue;
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end;
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end;
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end;
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A_TEST, A_CMP, A_Jcc:
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{ Skip over conditional jumps and relevant comparisons }
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Continue;
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A_MOVZX:
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if MatchOpType(taicpu(hp1), top_reg, top_reg) and
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SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(p).oper[1]^.reg) then
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begin
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{ Since the original register is being read as is, subsequent
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SHRs must not be merged at this point }
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DoNotMerge := True;
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if IsShrMovZFoldable(taicpu(p).opsize, taicpu(hp1).opsize, Shift) then
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begin
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if SuperRegistersEqual(taicpu(hp1).oper[0]^.reg, taicpu(hp1).oper[1]^.reg) then
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begin
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DebugMsg(SPeepholeOptimization + 'Removed MOVZX instruction since previous SHR makes it unnecessary (ShrMovz2Shr)', hp1);
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{ All the possible 1 bits are covered, so we can remove the AND }
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hp2 := tai(hp1.Previous);
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RemoveInstruction(hp1);
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hp1 := hp2;
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end
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else { Different register target }
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begin
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DebugMsg(SPeepholeOptimization + 'Converted MOVZX instruction to MOV since previous SHR makes zero-extension unnecessary (ShrMovz2ShrMov 2)', hp1);
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taicpu(hp1).opcode := A_MOV;
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setsubreg(taicpu(hp1).oper[0]^.reg, getsubreg(taicpu(hp1).oper[1]^.reg));
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case taicpu(hp1).opsize of
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S_BW:
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taicpu(hp1).opsize := S_W;
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S_BL, S_WL:
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taicpu(hp1).opsize := S_L;
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else
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InternalError(2022081503);
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end;
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end;
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end
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else if (Shift > 0) and
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(taicpu(p).opsize = S_W) and
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(taicpu(hp1).opsize = S_WL) and
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(taicpu(hp1).oper[0]^.reg = NR_AX) and
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(taicpu(hp1).oper[1]^.reg = NR_EAX) then
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begin
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{ Detect:
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shr x, %ax (x > 0)
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...
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movzwl %ax,%eax
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Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
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}
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DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via ShrMovz2ShrCwtl)', hp1);
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taicpu(hp1).opcode := A_CWDE;
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taicpu(hp1).clearop(0);
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taicpu(hp1).clearop(1);
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taicpu(hp1).ops := 0;
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end;
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{ Move onto the next instruction }
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Continue;
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end;
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A_SHL, A_SAL, A_SHR:
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if (taicpu(hp1).opsize <= LimitSize) and
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MatchOpType(taicpu(hp1), top_const, top_reg) and
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SuperRegistersEqual(taicpu(hp1).oper[1]^.reg, taicpu(p).oper[1]^.reg) then
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begin
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{ Make sure the sizes don't exceed the register size limit
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(measured by the shift value falling below the limit) }
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if taicpu(hp1).opsize < LimitSize then
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LimitSize := taicpu(hp1).opsize;
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if taicpu(hp1).opcode = A_SHR then
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Inc(Shift, taicpu(hp1).oper[0]^.val)
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else
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begin
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Dec(Shift, taicpu(hp1).oper[0]^.val);
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DoNotMerge := True;
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end;
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if Shift < topsize2memsize[taicpu(p).opsize] - topsize2memsize[LimitSize] then
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Exit;
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{ Since we've established that the combined shift is within
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limits, we can actually combine the adjacent SHR
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instructions even if they're different sizes }
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if not DoNotMerge and (taicpu(hp1).opcode = A_SHR) then
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begin
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hp2 := tai(hp1.Previous);
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DebugMsg(SPeepholeOptimization + 'ShrShr2Shr 2', p);
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Inc(taicpu(p).oper[0]^.val, taicpu(hp1).oper[0]^.val);
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RemoveInstruction(hp1);
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hp1 := hp2;
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end;
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{ Move onto the next instruction }
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Continue;
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end;
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else
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;
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end;
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Break;
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until False;
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end;
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@ -130,6 +130,8 @@ uses
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result:=OptPass1Sub(p);
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A_SHL,A_SAL:
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result:=OptPass1SHLSAL(p);
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A_SHR:
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result:=OptPass1SHR(p);
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A_FSTP,A_FISTP:
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result:=OptPass1FSTP(p);
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A_FLD:
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