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* several arm fixes

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git-svn-id: trunk@4742 -
This commit is contained in:
florian 2006-09-27 21:05:05 +00:00
parent 506f44dc7a
commit 67ba76f090
5 changed files with 66 additions and 49 deletions
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18
compiler/arm/cgcpu.pas
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@ -394,7 +394,7 @@ unit cgcpu;
OP_SHL: OP_SHL:
begin begin
if a>32 then if a>32 then
internalerror(200308291); internalerror(200308294);
if a<>0 then if a<>0 then
begin begin
shifterop_reset(so); shifterop_reset(so);
@ -422,7 +422,7 @@ unit cgcpu;
OP_SAR: OP_SAR:
begin begin
if a>32 then if a>32 then
internalerror(200308291); internalerror(200308295);
if a<>0 then if a<>0 then
begin begin
shifterop_reset(so); shifterop_reset(so);
@ -465,7 +465,7 @@ unit cgcpu;
else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a-1,l1) and not(cgsetflags or setflags) then else if (op in [OP_MUL,OP_IMUL]) and ispowerof2(a-1,l1) and not(cgsetflags or setflags) then
begin begin
if l1>32 then{roozbeh does this ever happen?} if l1>32 then{roozbeh does this ever happen?}
internalerror(200308291); internalerror(200308296);
shifterop_reset(so); shifterop_reset(so);
so.shiftmode:=SM_LSL; so.shiftmode:=SM_LSL;
so.shiftimm:=l1; so.shiftimm:=l1;
@ -844,7 +844,7 @@ unit cgcpu;
OS_S32: OS_S32:
oppostfix:=PF_None; oppostfix:=PF_None;
else else
InternalError(200308291); InternalError(200308297);
end; end;
if Ref.alignment<>0 then if Ref.alignment<>0 then
begin begin
@ -1020,7 +1020,15 @@ unit cgcpu;
LOC_FPUREGISTER,LOC_CFPUREGISTER: LOC_FPUREGISTER,LOC_CFPUREGISTER:
a_loadfpu_ref_reg(list,size,ref,hloc^.register); a_loadfpu_ref_reg(list,size,ref,hloc^.register);
LOC_REGISTER : LOC_REGISTER :
case hloc^.size of
OS_F32:
a_load_ref_reg(list,OS_32,OS_32,href,hloc^.register);
OS_64,
OS_F64:
cg64.a_param64_ref(list,href,paraloc);
else
a_load_ref_reg(list,hloc^.size,hloc^.size,href,hloc^.register); a_load_ref_reg(list,hloc^.size,hloc^.size,href,hloc^.register);
end;
LOC_REFERENCE : LOC_REFERENCE :
begin begin
reference_reset_base(href2,hloc^.reference.index,hloc^.reference.offset); reference_reset_base(href2,hloc^.reference.index,hloc^.reference.offset);
@ -1046,8 +1054,10 @@ unit cgcpu;
oppostfix:toppostfix; oppostfix:toppostfix;
begin begin
case size of case size of
OS_32,
OS_F32: OS_F32:
oppostfix:=PF_S; oppostfix:=PF_S;
OS_64,
OS_F64: OS_F64:
oppostfix:=PF_D; oppostfix:=PF_D;
OS_F80: OS_F80:

2
compiler/arm/cpupara.pas
View File

@ -288,7 +288,7 @@ unit cpupara;
OS_F32: OS_F32:
paraloc^.size:=OS_32; paraloc^.size:=OS_32;
OS_F64: OS_F64:
paraloc^.size:=OS_64; paraloc^.size:=OS_32;
else else
internalerror(2005082901); internalerror(2005082901);
end end

7
compiler/ncgcal.pas
View File

@ -76,6 +76,7 @@ implementation
uses uses
systems, systems,
cutils,verbose,globals, cutils,verbose,globals,
cpuinfo,
symconst,symtable,defutil,paramgr, symconst,symtable,defutil,paramgr,
cgbase,pass_2, cgbase,pass_2,
aasmbase,aasmtai,aasmdata, aasmbase,aasmtai,aasmdata,
@ -601,6 +602,12 @@ implementation
location.register:=cg.getintregister(current_asmdata.CurrAsmList,def_cgsize(resulttype.def)); location.register:=cg.getintregister(current_asmdata.CurrAsmList,def_cgsize(resulttype.def));
cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,def_cgsize(resulttype.def),procdefinition.funcretloc[callerside].register,location.register); cg.a_load_reg_reg(current_asmdata.CurrAsmList,cgsize,def_cgsize(resulttype.def),procdefinition.funcretloc[callerside].register,location.register);
end; end;
{$ifdef arm}
if (resulttype.def.deftype=floatdef) and (aktfputype in [fpu_fpa,fpu_fpa10,fpu_fpa11]) then
begin
location_force_mem(current_asmdata.CurrAsmList,location);
end;
{$endif arm}
end end
else else
begin begin

6
compiler/ncgutil.pas
View File

@ -1578,7 +1578,7 @@ implementation
paraloc : pcgparalocation; paraloc : pcgparalocation;
href : treference; href : treference;
sizeleft : aint; sizeleft : aint;
{$ifdef sparc} {$if defined(sparc) or defined(arm)}
tempref : treference; tempref : treference;
{$endif sparc} {$endif sparc}
begin begin
@ -1696,8 +1696,8 @@ implementation
end; end;
LOC_CFPUREGISTER : LOC_CFPUREGISTER :
begin begin
{$ifdef sparc} {$if defined(sparc) or defined(arm)}
{ Sparc passes floats in int registers, when loading to fpu register { Arm and Sparc passes floats in int registers, when loading to fpu register
we need a temp } we need a temp }
sizeleft := TCGSize2Size[currpara.initialloc.size]; sizeleft := TCGSize2Size[currpara.initialloc.size];
tg.GetTemp(list,sizeleft,tt_normal,tempref); tg.GetTemp(list,sizeleft,tt_normal,tempref);