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* improve RiscV assembler optimizer
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@ -332,7 +332,11 @@ implementation
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(taicpu(p).oper[2]^.typ=top_const) and
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(taicpu(p).oper[2]^.val=0) and
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GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1, [A_SUB,A_ADD,A_SLL,A_SLT,A_AND,A_OR{$ifdef riscv64}{$endif}]) and
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MatchInstruction(hp1, [A_SUB,A_ADD,A_SLL,A_SRL,A_SLT,A_AND,A_OR,
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A_ADDI,A_ANDI,A_ORI,A_SRAI,A_SRLI,A_SLLI,A_XORI
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{$ifdef riscv64},A_ADDIW,A_SLLIW,A_SRLIW,A_SRAIW,
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A_ADDW,A_SLLW,A_SRLW,A_SUBW,A_SRAW{$endif}]
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) and
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(taicpu(hp1).ops=3) and
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(MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[2]^) or MatchOperand(taicpu(p).oper[0]^,taicpu(hp1).oper[1]^)) and
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(not RegModifiedBetween(taicpu(p).oper[1]^.reg, p,hp1)) and
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@ -622,6 +626,13 @@ implementation
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RemoveInstr(p);
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result:=true;
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end
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else if (taicpu(p).oper[2]^.val=0) then
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begin
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{ this enables further optimizations }
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DebugMsg('Peephole S*LI x,y,0 to addi performed', p);
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taicpu(p).opcode:=A_ADDI;
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result:=true;
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end
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else
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result:=OptPass1OP(p);
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end;
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