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m68k: add support for OP_ROL/OP_ROR to a_op_reg_reg. this fixes m68k builds after 0af3f2a9

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This commit is contained in:
Karoly Balogh 2025-09-11 05:04:11 +02:00
parent 69611bba2d
commit 6a82ca8a1e
1 changed files with 30 additions and 12 deletions
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42
compiler/m68k/cgcpu.pas
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@ -1431,9 +1431,35 @@ unit cgcpu;
end;
list.concat(taicpu.op_reg_reg(opcode, opsize, src, dst));
end;
OP_AND,OP_OR,
OP_SAR,OP_SHL,
OP_SHR,OP_XOR:
OP_SAR,
OP_SHL,
OP_SHR:
OP_ROR,
OP_ROL:
begin
{ the compiler has code on the higher levels to try to prevent generating
ROR/ROL instructions on m68k CPUs that don't support it (ColdFire family) }
if op in [OP_ROR,OP_ROL] and
not CPUM68K_HAS_ROLROR in cpu_capabilites[current_settings.cputype]) then
internalerror(2025091101);
{ load to data registers }
hreg1 := force_to_dataregister(list, size, src);
hreg2 := force_to_dataregister(list, size, dst);
if not (CPUM68K_HAS_BYTEWORDMATH in cpu_capabilities[current_settings.cputype]) then
{ source for these ops are always modulo 64 on m68k,
so we don't need to extend the src register }
sign_extend(list, size, dst);
list.concat(taicpu.op_reg_reg(opcode, opsize, hreg1, hreg2));
{ move back result into destination register }
move_if_needed(list, size, hreg2, dst);
end;
OP_AND,
OP_OR,
OP_XOR:
begin
{ load to data registers }
hreg1 := force_to_dataregister(list, size, src);
@ -1441,15 +1467,7 @@ unit cgcpu;
if current_settings.cputype in cpu_coldfire then
begin
{ operation only allowed only a longword }
{!***************************************
in the case of shifts, the value to
shift by, should already be valid, so
no need to sign extend the value
!
}
if op in [OP_AND,OP_OR,OP_XOR] then
sign_extend(list, size, hreg1);
sign_extend(list, size, hreg1);
sign_extend(list, size, hreg2);
end;
list.concat(taicpu.op_reg_reg(opcode, opsize, hreg1, hreg2));