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* improved register usage
+ implemented second_cmp64bit
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@ -124,9 +124,10 @@ unit cgcpu;
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procedure tcgarm.init_register_allocators;
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begin
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inherited init_register_allocators;
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{ currently, we save R14 always, so we can use it }
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rg[R_INTREGISTER]:=trgcpu.create(R_INTREGISTER,R_SUBWHOLE,
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[RS_R0,RS_R1,RS_R2,RS_R3,RS_R4,RS_R5,RS_R6,RS_R7,RS_R8,
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RS_R9,RS_R10,RS_R12],first_int_imreg,[]);
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RS_R9,RS_R10,RS_R12,RS_R14],first_int_imreg,[]);
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rg[R_FPUREGISTER]:=trgcpu.create(R_FPUREGISTER,R_SUBNONE,
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[RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7],first_fpu_imreg,[]);
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rg[R_MMREGISTER]:=trgcpu.create(R_MMREGISTER,R_SUBNONE,
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@ -1207,7 +1208,11 @@ begin
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end.
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{
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$Log$
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Revision 1.34 2004-01-21 19:01:03 florian
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Revision 1.35 2004-01-22 01:47:15 florian
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* improved register usage
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+ implemented second_cmp64bit
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Revision 1.34 2004/01/21 19:01:03 florian
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* fixed handling of max. distance of pc relative symbols
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Revision 1.33 2004/01/21 15:41:56 florian
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@ -230,14 +230,47 @@ interface
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procedure tarmaddnode.second_cmp64bit;
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var
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unsigned : boolean;
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tmpreg : tregister;
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begin
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{$warning TODO 64bit compare}
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pass_left_right;
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force_reg_left_right(false,false);
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unsigned:=not(is_signed(left.resulttype.def)) or
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not(is_signed(right.resulttype.def));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned);
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{ operation requiring proper N, Z and C flags ? }
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if unsigned or (nodetype in [equaln,unequaln]) then
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begin
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exprasmlist.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo));
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exprasmlist.concat(setcondition(taicpu.op_reg_reg(A_CMP,left.location.register64.reghi,right.location.register64.reghi),C_EQ));
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end
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{ operation requiring proper N, V and C flags ? }
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else if nodetype in [gten,ltn] then
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begin
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tmpreg:=cg.getintregister(exprasmlist,location.size);
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exprasmlist.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,tmpreg,left.location.register64.reglo,right.location.register64.reglo),PF_S));
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exprasmlist.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,tmpreg,left.location.register64.reghi,right.location.register64.reghi),PF_S));
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cg.ungetregister(exprasmlist,tmpreg);
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end
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else
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{ operation requiring proper N, Z and V flags ? }
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begin
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{ this isn't possible so swap operands and use the "reverse" operation }
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tmpreg:=cg.getintregister(exprasmlist,location.size);
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exprasmlist.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SUB,tmpreg,right.location.register64.reglo,left.location.register64.reglo),PF_S));
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exprasmlist.concat(setoppostfix(taicpu.op_reg_reg_reg(A_SBC,tmpreg,right.location.register64.reghi,left.location.register64.reghi),PF_S));
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cg.ungetregister(exprasmlist,tmpreg);
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if location.resflags=F_GT then
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location.resflags:=F_LT
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else if location.resflags=F_LE then
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location.resflags:=F_GE
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else
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internalerror(200401221);
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end;
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release_reg_left_right;
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end;
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@ -281,7 +314,11 @@ begin
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end.
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{
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$Log$
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Revision 1.5 2003-11-02 14:30:03 florian
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Revision 1.6 2004-01-22 01:47:15 florian
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* improved register usage
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+ implemented second_cmp64bit
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Revision 1.5 2003/11/02 14:30:03 florian
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* fixed ARM for new reg. allocation scheme
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Revision 1.4 2003/09/01 15:11:16 florian
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