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Add missing NOP, and B instruction forms.
Move ThumbFunc flag from section to symbol. Make .w forms optional the other way around. If .w is explicitly put on an instruction the assembler should always chose a wide form. git-svn-id: branches/laksen/armiw@29341 -
This commit is contained in:
Jeppe Johansen
parent
de00a1d76d
commit
71cdedea82
@ -93,6 +93,7 @@ uses
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OT_REG64 = $00201008;
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OT_VREG = $00201010; { vector register }
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OT_REGF = $00201020; { coproc register }
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OT_REGS = $00201040; { special register with mask }
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OT_MEMORY = $00204000; { register number in 'basereg' }
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OT_MEM8 = $00204001;
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OT_MEM16 = $00204002;
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@ -1453,10 +1454,6 @@ implementation
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procedure gather_it_info(list: TAsmList);
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const
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opCount: array[A_IT..A_ITTTT] of longint =
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(1,2,2,3,3,3,3,
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4,4,4,4,4,4,4,4);
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var
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curtai: tai;
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in_it: boolean;
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@ -1479,7 +1476,7 @@ implementation
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else
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begin
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in_it:=true;
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it_count:=opCount[taicpu(curtai).opcode];
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it_count:=GetITLevels(taicpu(curtai).opcode);
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end;
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end;
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else
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@ -1502,8 +1499,51 @@ implementation
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end;
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end;
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{ Expands pseudo instructions ( mov r1,r2,lsl #4 -> lsl r1,r2,#4) }
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procedure expand_instructions(list: TAsmList);
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var
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curtai: tai;
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begin
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curtai:=tai(list.First);
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while assigned(curtai) do
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begin
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case curtai.typ of
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ait_instruction:
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begin
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case taicpu(curtai).opcode of
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A_MOV:
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begin
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if (taicpu(curtai).ops=3) and
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(taicpu(curtai).oper[2]^.typ=top_shifterop) then
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begin
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case taicpu(curtai).oper[2]^.shifterop^.shiftmode of
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SM_LSL: taicpu(curtai).opcode:=A_LSL;
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SM_LSR: taicpu(curtai).opcode:=A_LSR;
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SM_ASR: taicpu(curtai).opcode:=A_ASR;
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SM_ROR: taicpu(curtai).opcode:=A_ROR;
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SM_RRX: taicpu(curtai).opcode:=A_RRX;
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end;
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if taicpu(curtai).oper[2]^.shifterop^.rs=NR_NO then
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taicpu(curtai).loadconst(2, taicpu(curtai).oper[2]^.shifterop^.shiftimm)
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else
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taicpu(curtai).loadreg(2, taicpu(curtai).oper[2]^.shifterop^.rs);
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end;
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end;
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end;
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end;
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end;
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curtai:=tai(curtai.Next);
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end;
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end;
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procedure finalizearmcode(list, listtoinsert: TAsmList);
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begin
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expand_instructions(list);
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{ Do Thumb-2 16bit -> 32bit transformations }
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if GenerateThumb2Code then
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begin
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@ -1712,6 +1752,9 @@ implementation
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else
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if (ot and OT_FPUREG)=OT_FPUREG then
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s:=s+'fpureg'
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else
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if (ot and OT_REGS)=OT_REGS then
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s:=s+'sreg'
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else
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if (ot and OT_REGF)=OT_REGF then
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s:=s+'creg'
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@ -2109,6 +2152,10 @@ implementation
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begin
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ot:=OT_CONDITION;
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end;
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top_specialreg:
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begin
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ot:=OT_REGS;
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end;
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else
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begin writeln(typ);
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internalerror(200402261); end;
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@ -2166,10 +2213,10 @@ implementation
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end;
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{ Check wideformat flag }
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if ((p^.flags and IF_WIDE)<>0) <> wideformat then
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if wideformat and ((p^.flags and IF_WIDE)=0) then
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begin
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{matches:=0;
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exit;}
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matches:=0;
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exit;
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end;
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{ Check that no spurious colons or TOs are present }
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@ -4079,14 +4126,27 @@ implementation
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if oper[0]^.typ=top_const then
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begin
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if insentry^.code[0]=#$63 then
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bytes:=bytes or ((oper[0]^.val shr 1) and $FF)
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bytes:=bytes or (((oper[0]^.val shr 1)-1) and $FF)
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else
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bytes:=bytes or ((oper[0]^.val shr 1) and $3FF);
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bytes:=bytes or (((oper[0]^.val shr 1)-1) and $3FF);
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end
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else if oper[0]^.typ=top_reg then
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begin
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bytes:=bytes or (getsupreg(oper[0]^.reg) shl 3);
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end;
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end
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else if oper[0]^.typ=top_ref then
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begin
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offset:=0;
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currsym:=objdata.symbolref(oper[0]^.ref^.symbol);
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if assigned(currsym) then
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offset:=currsym.offset-insoffset-8;
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offset:=offset+oper[0]^.ref^.offset;
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if insentry^.code[0]=#$63 then
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bytes:=bytes or (((offset+4) shr 1) and $FF)
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else
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bytes:=bytes or (((offset+4) shr 1) and $7FF);
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end
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end;
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#$64: { Thumb: Special encodings }
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begin
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@ -4171,7 +4231,7 @@ implementation
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else
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bytes:=bytes or ((oper[1]^.val shr ord(insentry^.code[3])) and $FF);
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end;
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#$68: { Thumb CB{N}Z }
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#$68: { Thumb CB[N]Z }
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begin
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bytelen:=2;
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bytes:=0;
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@ -145,11 +145,11 @@ reg32,reg32,reg32,shifterop \x6\x0\x00 ARM32,ARMv4
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reg32,reg32,immshifter \x7\x2\x00 ARM32,ARMv4
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[Bcc]
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imm32 \x62\xE0\x0 THUMB,ARMv4T
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imm24 \x62\xE0\x0 THUMB,ARMv4T
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immshifter \x62\xE0\x0 THUMB,ARMv4T
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mem32 \x62\xE0\x0 THUMB,ARMv4T
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imm32 \x63\xD0\x0 THUMB,ARMv4T
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imm24 \x63\xD0\x0 THUMB,ARMv4T
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immshifter \x63\xD0\x0 THUMB,ARMv4T
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mem32 \x63\xD0\x0 THUMB,ARMv4T
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@ -361,6 +361,7 @@ reg32,regf \x10\x01\x0F ARM32,ARMv4
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[MSRcc]
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regf,reg32 \x12\x01\x28\xF0 ARM32,ARMv4
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regf,immshifter \x13\x03\x28\xF0 ARM32,ARMv4
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regs,immshifter \x13\x03\x28\xF0 ARM32,ARMv4
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[MULcc]
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reglo,reglo,reglo \x64\x43\x40 THUMB,ARMv4T
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@ -396,6 +397,8 @@ vreg,reg32,reg32 \x40\xC\x40\xB\x10 ARM32,VFPv2
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[NOP]
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void \x61\xBF\x0 THUMB,ARMv6T2
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void \x2F\x03\x20\xF0\x0 ARM32,ARMv6K
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; Before ARMv6K use mov r0,r0
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void \x2F\xE1\xA0\x0\x0 ARM32,ARMv4
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[ORNcc]
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reg32,reg32,immshifter \x80\xF0\x60\x0\x0 THUMB32,ARMv6T2
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@ -1,2 +1,2 @@
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{ don't edit, this file is generated from armins.dat }
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651;
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653;
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@ -255,7 +255,7 @@
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(
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opcode : A_B;
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ops : 1;
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optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
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optypes : (ot_immediate24,ot_none,ot_none,ot_none,ot_none,ot_none);
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code : #98#224#0;
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flags : if_thumb or if_armv4t
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),
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@ -276,7 +276,7 @@
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(
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opcode : A_B;
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ops : 1;
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optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
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optypes : (ot_immediate24,ot_none,ot_none,ot_none,ot_none,ot_none);
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code : #99#208#0;
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flags : if_thumb or if_armv4t
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),
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@ -1085,6 +1085,13 @@
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code : #19#3#40#240;
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flags : if_arm32 or if_armv4
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),
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(
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opcode : A_MSR;
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ops : 2;
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optypes : (ot_regs,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
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code : #19#3#40#240;
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flags : if_arm32 or if_armv4
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),
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(
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opcode : A_MUL;
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ops : 3;
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@ -1225,6 +1232,13 @@
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code : #47#3#32#240#0;
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flags : if_arm32 or if_armv6k
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),
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(
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opcode : A_NOP;
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ops : 0;
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optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
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code : #47#225#160#0#0;
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flags : if_arm32 or if_armv4
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),
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(
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opcode : A_ORN;
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ops : 3;
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@ -591,7 +591,6 @@ unit cpubase;
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var
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t : aint;
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i : longint;
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imm : byte;
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begin
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{Loading 0-255 is simple}
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if (d and $FF) = d then
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@ -611,7 +610,7 @@ unit cpubase;
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result:=false;
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for i:=1 to 31 do
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begin
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t:=RolDWord(imm,i);
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t:=RolDWord(d,i);
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if ((t and $FF)=t) and
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((t and $80)=$80) then
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begin
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@ -172,6 +172,10 @@ interface
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{ Darwin asm is using indirect symbols resolving }
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indsymbol : TObjSymbol;
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{$ifdef ARM}
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ThumbFunc : boolean;
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{$endif ARM}
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constructor create(AList:TFPHashObjectList;const AName:string);
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function address:aword;
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procedure SetAddress(apass:byte;aobjsec:TObjSection;abind:TAsmsymbind;atyp:Tasmsymtype);
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@ -233,9 +237,6 @@ interface
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ExeSection : TExeSection;
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USed : Boolean;
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VTRefList : TFPObjectList;
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{$ifdef ARM}
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ThumbFunc : boolean;
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{$endif ARM}
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constructor create(AList:TFPHashObjectList;const Aname:string;Aalign:shortint;Aoptions:TObjSectionOptions);virtual;
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destructor destroy;override;
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function write(const d;l:aword):aword;
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@ -1140,10 +1141,6 @@ implementation
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begin
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result:=CObjSection.create(FObjSectionList,aname,aalign,aoptions);
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result.ObjData:=self;
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{$ifdef ARM}
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result.ThumbFunc:=ThumbFunc;
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ThumbFunc:=false;
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{$endif ARM}
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end;
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FCurrObjSec:=result;
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end;
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@ -1181,6 +1178,11 @@ implementation
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result:=TObjSymbol(FObjSymbolList.Find(aname));
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if not assigned(result) then
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result:=TObjSymbol.Create(FObjSymbolList,aname);
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{$ifdef ARM}
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result.ThumbFunc:=ThumbFunc;
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ThumbFunc:=false;
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{$endif ARM}
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end;
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@ -970,8 +970,7 @@ implementation
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elfsym.st_value:=objsym.address;
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{$ifdef ARM}
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if (objsym.typ=AT_FUNCTION) and
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objsym.objsection.ThumbFunc then
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if objsym.ThumbFunc then
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inc(elfsym.st_value);
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{$endif ARM}
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@ -15,7 +15,7 @@
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**********************************************************************}
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{$asmmode gas}
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{$asmmode divided}
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{$ifndef FPC_SYSTEM_HAS_MOVE}
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{$define FPC_SYSTEM_FPC_MOVE}
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@ -15,7 +15,7 @@
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**********************************************************************}
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{$asmmode gas}
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{$asmmode divided}
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{$ifndef FPC_SYSTEM_HAS_MOVE}
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{$define FPC_SYSTEM_FPC_MOVE}
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