mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-17 00:19:38 +02:00
+ support for handling OS_128/OS_S128 on 64 Bit CPUs as far as needed for method pointers in registers
git-svn-id: trunk@22344 -
This commit is contained in:
florian
parent
4514a55ec6
commit
7361e19799
compiler
@ -738,6 +738,9 @@ interface
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varsym : tsym;
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constructor create(sym : tsym;loc : tregister);
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constructor create64(sym : tsym;loc,lochi : tregister);
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{$ifdef cpu64bitalu}
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constructor create128(sym : tsym;loc,lochi : tregister);
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{$endif cpu64bitalu}
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constructor ppuload(t:taitype;ppufile:tcompilerppufile);override;
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procedure ppuwrite(ppufile:tcompilerppufile);override;
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procedure buildderefimpl;override;
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@ -917,7 +920,7 @@ implementation
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end;
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constructor tai_varloc.create64(sym: tsym; loc: tregister;lochi : tregister);
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constructor tai_varloc.create64(sym: tsym; loc, lochi: tregister);
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begin
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inherited Create;
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typ:=ait_varloc;
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@ -927,6 +930,18 @@ implementation
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end;
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{$ifdef cpu64bitalu}
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constructor tai_varloc.create128(sym: tsym; loc, lochi: tregister);
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begin
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inherited Create;
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typ:=ait_varloc;
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newlocation:=loc;
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newlocationhi:=lochi;
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varsym:=sym;
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end;
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{$endif cpu64bitalu}
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constructor tai_varloc.ppuload(t: taitype; ppufile: tcompilerppufile);
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begin
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inherited ppuload(t, ppufile);
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@ -162,6 +162,7 @@ end;
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procedure create_codegen;
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begin
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cg:=tcgalpha.create;
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cg128:=tcg128.create;
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end;
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end.
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@ -61,7 +61,6 @@ unit cg64f32;
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procedure a_load64_reg_loc(list : TAsmList;reg : tregister64;const l : tlocation);override;
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procedure a_load64high_reg_ref(list : TAsmList;reg : tregister;const ref : treference);override;
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procedure a_load64low_reg_ref(list : TAsmList;reg : tregister;const ref : treference);override;
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procedure a_load64high_ref_reg(list : TAsmList;const ref : treference;reg : tregister);override;
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@ -366,8 +365,6 @@ unit cg64f32;
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end;
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procedure tcg64f32.a_load64_subsetref_subsetref(list: TAsmlist; const fromsref, tosref: tsubsetreference);
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var
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@ -209,6 +209,9 @@ interface
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{ A type to store register locations for 64 Bit values. }
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{$ifdef cpu64bitalu}
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tregister64 = tregister;
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tregister128 = record
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reglo,reghi : tregister;
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end;
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{$else cpu64bitalu}
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tregister64 = record
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reglo,reghi : tregister;
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@ -594,6 +597,11 @@ implementation
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OS_NO,OS_8,OS_16,OS_NO,OS_32,OS_NO,OS_NO,OS_NO,OS_64
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);
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begin
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{$ifdef cpu64bitalu}
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if a=16 then
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result:=OS_128
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else
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{$endif cpu64bitalu}
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if a>8 then
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result:=OS_NO
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else
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@ -458,7 +458,25 @@ unit cgobj;
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function g_indirect_sym_load(list:TAsmList;const symname: string; const flags: tindsymflags): tregister;virtual;
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end;
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{$ifndef cpu64bitalu}
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{$ifdef cpu64bitalu}
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{ This class implements an abstract code generator class
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for 128 Bit operations, it applies currently only to 64 Bit CPUs and supports only simple operations
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}
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tcg128 = class
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procedure a_load128_reg_reg(list : TAsmList;regsrc,regdst : tregister128);virtual;
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procedure a_load128_reg_ref(list : TAsmList;reg : tregister128;const ref : treference);virtual;
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procedure a_load128_loc_ref(list : TAsmList;const l : tlocation;const ref : treference);virtual;
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procedure a_load128_reg_loc(list : TAsmList;reg : tregister128;const l : tlocation);virtual;
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procedure a_load128_loc_cgpara(list : TAsmList;const l : tlocation;const paraloc : TCGPara);virtual;
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procedure a_load128_ref_cgpara(list: TAsmList; const r: treference;const paraloc: tcgpara);
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procedure a_load128_reg_cgpara(list: TAsmList; reg: tregister128;const paraloc: tcgpara);
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end;
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{ Creates a tregister128 record from 2 64 Bit registers. }
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function joinreg128(reglo,reghi : tregister) : tregister128;
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{$else cpu64bitalu}
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{# @abstract(Abstract code generator for 64 Bit operations)
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This class implements an abstract code generator class
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for 64 Bit operations.
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@ -474,7 +492,6 @@ unit cgobj;
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procedure a_load64_const_loc(list : TAsmList;value : int64;const l : tlocation);virtual;abstract;
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procedure a_load64_reg_loc(list : TAsmList;reg : tregister64;const l : tlocation);virtual;abstract;
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procedure a_load64_subsetref_reg(list : TAsmList; const sref: tsubsetreference; destreg: tregister64);virtual;abstract;
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procedure a_load64_reg_subsetref(list : TAsmList; fromreg: tregister64; const sref: tsubsetreference);virtual;abstract;
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procedure a_load64_const_subsetref(list: TAsmlist; a: int64; const sref: tsubsetreference);virtual;abstract;
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@ -537,10 +554,13 @@ unit cgobj;
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{$endif cpu64bitalu}
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var
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{# Main code generator class }
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{ Main code generator class }
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cg : tcg;
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{$ifndef cpu64bitalu}
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{# Code generator class for all operations working with 64-Bit operands }
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{$ifdef cpu64bitalu}
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{ Code generator class for all operations working with 128-Bit operands }
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cg128 : tcg128;
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{$else cpu64bitalu}
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{ Code generator class for all operations working with 64-Bit operands }
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cg64 : tcg64;
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{$endif cpu64bitalu}
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@ -556,7 +576,6 @@ implementation
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tgobj,cutils,procinfo,
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ncgrtti;
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{*****************************************************************************
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basic functionallity
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******************************************************************************}
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@ -2508,6 +2527,204 @@ implementation
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internalerror(2006082211);
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end;
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end;
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{$else cpu64bitalu}
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function joinreg128(reglo, reghi: tregister): tregister128;
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begin
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result.reglo:=reglo;
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result.reghi:=reghi;
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end;
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procedure splitparaloc128(const cgpara:tcgpara;var cgparalo,cgparahi:tcgpara);
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var
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paraloclo,
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paralochi : pcgparalocation;
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begin
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if not(cgpara.size in [OS_128,OS_S128]) then
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internalerror(2012090604);
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if not assigned(cgpara.location) then
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internalerror(2012090605);
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{ init lo/hi para }
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cgparahi.reset;
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if cgpara.size=OS_S128 then
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cgparahi.size:=OS_S64
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else
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cgparahi.size:=OS_64;
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cgparahi.intsize:=8;
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cgparahi.alignment:=cgpara.alignment;
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paralochi:=cgparahi.add_location;
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cgparalo.reset;
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cgparalo.size:=OS_64;
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cgparalo.intsize:=8;
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cgparalo.alignment:=cgpara.alignment;
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paraloclo:=cgparalo.add_location;
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{ 2 parameter fields? }
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if assigned(cgpara.location^.next) then
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begin
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{ Order for multiple locations is always
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paraloc^ -> high
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paraloc^.next -> low }
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if (target_info.endian=ENDIAN_BIG) then
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begin
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{ paraloc^ -> high
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paraloc^.next -> low }
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move(cgpara.location^,paralochi^,sizeof(paralochi^));
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move(cgpara.location^.next^,paraloclo^,sizeof(paraloclo^));
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end
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else
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begin
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{ paraloc^ -> low
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paraloc^.next -> high }
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move(cgpara.location^,paraloclo^,sizeof(paraloclo^));
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move(cgpara.location^.next^,paralochi^,sizeof(paralochi^));
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end;
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end
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else
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begin
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{ single parameter, this can only be in memory }
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if cgpara.location^.loc<>LOC_REFERENCE then
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internalerror(2012090606);
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move(cgpara.location^,paraloclo^,sizeof(paraloclo^));
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move(cgpara.location^,paralochi^,sizeof(paralochi^));
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{ for big endian low is at +8, for little endian high }
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if target_info.endian = endian_big then
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begin
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inc(cgparalo.location^.reference.offset,8);
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cgparalo.alignment:=newalignment(cgparalo.alignment,8);
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end
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else
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begin
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inc(cgparahi.location^.reference.offset,8);
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cgparahi.alignment:=newalignment(cgparahi.alignment,8);
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end;
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end;
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{ fix size }
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paraloclo^.size:=cgparalo.size;
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paraloclo^.next:=nil;
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paralochi^.size:=cgparahi.size;
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paralochi^.next:=nil;
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end;
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procedure tcg128.a_load128_reg_reg(list: TAsmList; regsrc,
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regdst: tregister128);
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begin
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cg.a_load_reg_reg(list,OS_64,OS_64,regsrc.reglo,regdst.reglo);
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cg.a_load_reg_reg(list,OS_64,OS_64,regsrc.reghi,regdst.reghi);
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end;
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procedure tcg128.a_load128_reg_ref(list: TAsmList; reg: tregister128;
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const ref: treference);
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var
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tmpreg: tregister;
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tmpref: treference;
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begin
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if target_info.endian = endian_big then
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begin
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tmpreg:=reg.reglo;
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reg.reglo:=reg.reghi;
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reg.reghi:=tmpreg;
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end;
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cg.a_load_reg_ref(list,OS_64,OS_64,reg.reglo,ref);
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tmpref := ref;
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inc(tmpref.offset,8);
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cg.a_load_reg_ref(list,OS_64,OS_64,reg.reghi,tmpref);
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end;
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procedure tcg128.a_load128_loc_ref(list: TAsmList; const l: tlocation;
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const ref: treference);
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begin
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case l.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_load128_reg_ref(list,l.register128,ref);
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{ not yet implemented:
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LOC_CONSTANT :
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a_load128_const_ref(list,l.value128,ref);
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LOC_SUBSETREF, LOC_CSUBSETREF:
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a_load64_subsetref_ref(list,l.sref,ref); }
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else
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internalerror(201209061);
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end;
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end;
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procedure tcg128.a_load128_reg_loc(list: TAsmList; reg: tregister128;
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const l: tlocation);
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begin
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case l.loc of
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LOC_REFERENCE, LOC_CREFERENCE:
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a_load128_reg_ref(list,reg,l.reference);
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LOC_REGISTER,LOC_CREGISTER:
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a_load128_reg_reg(list,reg,l.register128);
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{ not yet implemented:
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LOC_SUBSETREF, LOC_CSUBSETREF:
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a_load64_reg_subsetref(list,reg,l.sref);
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LOC_MMREGISTER, LOC_CMMREGISTER:
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a_loadmm_intreg64_reg(list,l.size,reg,l.register); }
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else
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internalerror(201209062);
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end;
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end;
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procedure tcg128.a_load128_loc_cgpara(list: TAsmList; const l: tlocation;
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const paraloc: TCGPara);
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begin
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case l.loc of
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LOC_REGISTER,
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LOC_CREGISTER :
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a_load128_reg_cgpara(list,l.register128,paraloc);
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{not yet implemented:
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LOC_CONSTANT :
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a_load128_const_cgpara(list,l.value64,paraloc);
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}
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LOC_CREFERENCE,
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LOC_REFERENCE :
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a_load128_ref_cgpara(list,l.reference,paraloc);
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else
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internalerror(2012090603);
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end;
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end;
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procedure tcg128.a_load128_reg_cgpara(list : TAsmList;reg : tregister128;const paraloc : tcgpara);
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var
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tmplochi,tmploclo: tcgpara;
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begin
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tmploclo.init;
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tmplochi.init;
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splitparaloc128(paraloc,tmploclo,tmplochi);
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cg.a_load_reg_cgpara(list,OS_64,reg.reghi,tmplochi);
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cg.a_load_reg_cgpara(list,OS_64,reg.reglo,tmploclo);
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tmploclo.done;
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tmplochi.done;
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end;
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procedure tcg128.a_load128_ref_cgpara(list : TAsmList;const r : treference;const paraloc : tcgpara);
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var
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tmprefhi,tmpreflo : treference;
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tmploclo,tmplochi : tcgpara;
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begin
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tmploclo.init;
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tmplochi.init;
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splitparaloc128(paraloc,tmploclo,tmplochi);
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tmprefhi:=r;
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tmpreflo:=r;
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if target_info.endian=endian_big then
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inc(tmpreflo.offset,8)
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else
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inc(tmprefhi.offset,8);
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cg.a_load_ref_cgpara(list,OS_64,tmprefhi,tmplochi);
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cg.a_load_ref_cgpara(list,OS_64,tmpreflo,tmploclo);
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tmploclo.done;
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tmplochi.done;
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end;
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{$endif cpu64bitalu}
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function asmsym2indsymflags(sym: TAsmSymbol): tindsymflags;
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@ -2523,7 +2740,10 @@ implementation
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begin
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cg.free;
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cg:=nil;
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{$ifndef cpu64bitalu}
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{$ifdef cpu64bitalu}
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cg128.free;
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cg128:=nil;
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{$else cpu64bitalu}
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cg64.free;
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cg64:=nil;
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{$endif cpu64bitalu}
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@ -127,7 +127,10 @@ unit cgutils;
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registeralias : tregister;
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{$endif m68k}
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);
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{$ifndef cpu64bitalu}
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{$ifdef cpu64bitalu}
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{ overlay a 128 Bit register type }
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2 : (register128 : tregister128);
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{$else cpu64bitalu}
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{ overlay a 64 Bit register type }
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2 : (register64 : tregister64);
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{$endif cpu64bitalu}
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@ -1200,11 +1200,15 @@ implementation
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LOC_CREGISTER :
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begin
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tg.gethltemp(list,size,size.size,tt_normal,r);
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{$ifndef cpu64bitalu}
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{$ifdef cpu64bitalu}
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if l.size in [OS_128,OS_S128] then
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cg128.a_load128_loc_ref(list,l,r)
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else
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{$else cpu64bitalu}
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if l.size in [OS_64,OS_S64] then
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cg64.a_load64_loc_ref(list,l,r)
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else
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{$endif not cpu64bitalu}
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{$endif cpu64bitalu}
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a_load_loc_ref(list,size,size,l,r);
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location_reset_ref(l,LOC_REFERENCE,l.size,0);
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l.reference:=r;
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@ -1329,10 +1333,8 @@ implementation
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end;
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procedure thlcg2ll.gen_load_loc_cgpara(list: TAsmList; vardef: tdef; const l: tlocation; const cgpara: tcgpara);
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{$ifndef cpu64bitalu}
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var
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tmploc: tlocation;
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{$endif not cpu64bitalu}
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begin
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{ Handle Floating point types differently
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@ -1355,19 +1357,28 @@ implementation
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LOC_REFERENCE,
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LOC_CREFERENCE :
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begin
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{$ifndef cpu64bitalu}
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{$ifdef cpu64bitalu}
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{ use cg128 only if no "chained" location is used }
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if (l.size in [OS_128,OS_S128]) and (cgpara.Size in [OS_128,OS_S128]) then
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cg128.a_load128_loc_cgpara(list,l,cgpara)
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else
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{$else cpu64bitalu}
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{ use cg64 only for int64, not for 8 byte records }
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if (l.size in [OS_64,OS_S64]) and (cgpara.Size in [OS_64,OS_S64]) then
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cg64.a_load64_loc_cgpara(list,l,cgpara)
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else
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{$endif not cpu64bitalu}
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{$endif cpu64bitalu}
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begin
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{$ifndef cpu64bitalu}
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{ Only a_load_ref_cgpara supports multiple locations, when the
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value is still a const or in a register then write it
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to a reference first. This situation can be triggered
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by typecasting an int64 constant to a record of 8 bytes }
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{$ifdef cpu64bitalu}
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if l.size in [OS_128,OS_S128] then
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{$else cpu64bitalu}
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if l.size in [OS_64,OS_S64] then
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{$endif cpu64bitalu}
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begin
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tmploc:=l;
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location_force_mem(list,tmploc,vardef);
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@ -1379,7 +1390,6 @@ implementation
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location_freetemp(list,tmploc);
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end
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else
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{$endif not cpu64bitalu}
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a_load_loc_cgpara(list,vardef,l,cgpara);
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end;
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end;
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||||
|
||||
@ -842,13 +842,18 @@ implementation
|
||||
LOC_REGISTER,
|
||||
LOC_CREGISTER :
|
||||
begin
|
||||
{$ifndef cpu64bitalu}
|
||||
{$ifdef cpu64bitalu}
|
||||
if left.location.size in [OS_128,OS_S128] then
|
||||
cg128.a_load128_reg_loc(current_asmdata.CurrAsmList,
|
||||
right.location.register128,left.location)
|
||||
else
|
||||
{$else cpu64bitalu}
|
||||
{ also OS_F64 in case of mmreg -> intreg }
|
||||
if left.location.size in [OS_64,OS_S64,OS_F64] then
|
||||
cg64.a_load64_reg_loc(current_asmdata.CurrAsmList,
|
||||
right.location.register64,left.location)
|
||||
else
|
||||
{$endif not cpu64bitalu}
|
||||
{$endif cpu64bitalu}
|
||||
hlcg.a_load_reg_loc(current_asmdata.CurrAsmList,right.resultdef,left.resultdef,right.location.register,left.location);
|
||||
end;
|
||||
LOC_FPUREGISTER,
|
||||
@ -1274,11 +1279,15 @@ implementation
|
||||
end;
|
||||
else
|
||||
begin
|
||||
{$ifndef cpu64bitalu}
|
||||
{$ifdef cpu64bitalu}
|
||||
if hp.left.location.size in [OS_128,OS_S128] then
|
||||
cg128.a_load128_loc_ref(current_asmdata.CurrAsmList,hp.left.location,href)
|
||||
else
|
||||
{$else cpu64bitalu}
|
||||
if hp.left.location.size in [OS_64,OS_S64] then
|
||||
cg64.a_load64_loc_ref(current_asmdata.CurrAsmList,hp.left.location,href)
|
||||
else
|
||||
{$endif not cpu64bitalu}
|
||||
{$endif cpu64bitalu}
|
||||
hlcg.a_load_loc_ref(current_asmdata.CurrAsmList,eledef,eledef,hp.left.location,href);
|
||||
end;
|
||||
end;
|
||||
|
||||
@ -1638,9 +1638,7 @@ implementation
|
||||
preplaceregrec = ^treplaceregrec;
|
||||
treplaceregrec = record
|
||||
old, new: tregister;
|
||||
{$ifndef cpu64bitalu}
|
||||
oldhi, newhi: tregister;
|
||||
{$endif not cpu64bitalu}
|
||||
ressym: tsym;
|
||||
{ moved sym }
|
||||
sym : tsym;
|
||||
@ -1665,7 +1663,15 @@ implementation
|
||||
(tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMXREGISTER,LOC_CMMREGISTER]) and
|
||||
(tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register = rr^.old) then
|
||||
begin
|
||||
{$ifndef cpu64bitalu}
|
||||
{$ifdef cpu64bitalu}
|
||||
{ it's possible a 128 bit location was shifted and/xor typecasted }
|
||||
{ in a 64 bit value, so only 1 register was left in the location }
|
||||
if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.size in [OS_128,OS_S128]) then
|
||||
if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register128.reghi = rr^.oldhi) then
|
||||
tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register128.reghi := rr^.newhi
|
||||
else
|
||||
exit;
|
||||
{$else cpu64bitalu}
|
||||
{ it's possible a 64 bit location was shifted and/xor typecasted }
|
||||
{ in a 32 bit value, so only 1 register was left in the location }
|
||||
if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.size in [OS_64,OS_S64]) then
|
||||
@ -1673,7 +1679,7 @@ implementation
|
||||
tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register64.reghi := rr^.newhi
|
||||
else
|
||||
exit;
|
||||
{$endif not cpu64bitalu}
|
||||
{$endif cpu64bitalu}
|
||||
tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register := rr^.new;
|
||||
rr^.sym := tabstractnormalvarsym(tloadnode(n).symtableentry);
|
||||
result := fen_norecurse_true;
|
||||
@ -1685,7 +1691,15 @@ implementation
|
||||
(ttemprefnode(n).tempinfo^.location.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMXREGISTER,LOC_CMMREGISTER]) and
|
||||
(ttemprefnode(n).tempinfo^.location.register = rr^.old) then
|
||||
begin
|
||||
{$ifndef cpu64bitalu}
|
||||
{$ifdef cpu64bitalu}
|
||||
{ it's possible a 128 bit location was shifted and/xor typecasted }
|
||||
{ in a 64 bit value, so only 1 register was left in the location }
|
||||
if (ttemprefnode(n).tempinfo^.location.size in [OS_128,OS_S128]) then
|
||||
if (ttemprefnode(n).tempinfo^.location.register128.reghi = rr^.oldhi) then
|
||||
ttemprefnode(n).tempinfo^.location.register128.reghi := rr^.newhi
|
||||
else
|
||||
exit;
|
||||
{$else cpu64bitalu}
|
||||
{ it's possible a 64 bit location was shifted and/xor typecasted }
|
||||
{ in a 32 bit value, so only 1 register was left in the location }
|
||||
if (ttemprefnode(n).tempinfo^.location.size in [OS_64,OS_S64]) then
|
||||
@ -1693,7 +1707,7 @@ implementation
|
||||
ttemprefnode(n).tempinfo^.location.register64.reghi := rr^.newhi
|
||||
else
|
||||
exit;
|
||||
{$endif not cpu64bitalu}
|
||||
{$endif cpu64bitalu}
|
||||
ttemprefnode(n).tempinfo^.location.register := rr^.new;
|
||||
result := fen_norecurse_true;
|
||||
end;
|
||||
@ -1725,13 +1739,19 @@ implementation
|
||||
rr.old := n.location.register;
|
||||
rr.ressym := nil;
|
||||
rr.sym := nil;
|
||||
{$ifndef cpu64bitalu}
|
||||
rr.oldhi := NR_NO;
|
||||
{$endif not cpu64bitalu}
|
||||
case n.location.loc of
|
||||
LOC_CREGISTER:
|
||||
begin
|
||||
{$ifndef cpu64bitalu}
|
||||
{$ifdef cpu64bitalu}
|
||||
if (n.location.size in [OS_128,OS_S128]) then
|
||||
begin
|
||||
rr.oldhi := n.location.register128.reghi;
|
||||
rr.new := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
||||
rr.newhi := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
||||
end
|
||||
else
|
||||
{$else cpu64bitalu}
|
||||
if (n.location.size in [OS_64,OS_S64]) then
|
||||
begin
|
||||
rr.oldhi := n.location.register64.reghi;
|
||||
@ -1739,7 +1759,7 @@ implementation
|
||||
rr.newhi := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
||||
end
|
||||
else
|
||||
{$endif not cpu64bitalu}
|
||||
{$endif cpu64bitalu}
|
||||
rr.new := cg.getintregister(current_asmdata.CurrAsmList,n.location.size);
|
||||
end;
|
||||
LOC_CFPUREGISTER:
|
||||
@ -1769,11 +1789,15 @@ implementation
|
||||
case n.location.loc of
|
||||
LOC_CREGISTER:
|
||||
begin
|
||||
{$ifndef cpu64bitalu}
|
||||
{$ifdef cpu64bitalu}
|
||||
if (n.location.size in [OS_128,OS_S128]) then
|
||||
cg128.a_load128_reg_reg(list,n.location.register128,joinreg128(rr.new,rr.newhi))
|
||||
else
|
||||
{$else cpu64bitalu}
|
||||
if (n.location.size in [OS_64,OS_S64]) then
|
||||
cg64.a_load64_reg_reg(list,n.location.register64,joinreg64(rr.new,rr.newhi))
|
||||
else
|
||||
{$endif not cpu64bitalu}
|
||||
{$endif cpu64bitalu}
|
||||
cg.a_load_reg_reg(list,n.location.size,n.location.size,n.location.register,rr.new);
|
||||
end;
|
||||
LOC_CFPUREGISTER:
|
||||
@ -1789,7 +1813,16 @@ implementation
|
||||
end;
|
||||
|
||||
{ now that we've change the loadn/temp, also change the node result location }
|
||||
{$ifndef cpu64bitalu}
|
||||
{$ifdef cpu64bitalu}
|
||||
if (n.location.size in [OS_128,OS_S128]) then
|
||||
begin
|
||||
n.location.register128.reglo := rr.new;
|
||||
n.location.register128.reghi := rr.newhi;
|
||||
if assigned(rr.sym) then
|
||||
list.concat(tai_varloc.create128(rr.sym,rr.new,rr.newhi));
|
||||
end
|
||||
else
|
||||
{$else cpu64bitalu}
|
||||
if (n.location.size in [OS_64,OS_S64]) then
|
||||
begin
|
||||
n.location.register64.reglo := rr.new;
|
||||
@ -1798,7 +1831,7 @@ implementation
|
||||
list.concat(tai_varloc.create64(rr.sym,rr.new,rr.newhi));
|
||||
end
|
||||
else
|
||||
{$endif not cpu64bitalu}
|
||||
{$endif cpu64bitalu}
|
||||
begin
|
||||
n.location.register := rr.new;
|
||||
if assigned(rr.sym) then
|
||||
@ -1825,14 +1858,21 @@ implementation
|
||||
case localloc.loc of
|
||||
LOC_CREGISTER :
|
||||
if (pi_has_label in current_procinfo.flags) then
|
||||
{$ifndef cpu64bitalu}
|
||||
{$ifdef cpu64bitalu}
|
||||
if def_cgsize(vardef) in [OS_128,OS_S128] then
|
||||
begin
|
||||
cg.a_reg_sync(list,localloc.register128.reglo);
|
||||
cg.a_reg_sync(list,localloc.register128.reghi);
|
||||
end
|
||||
else
|
||||
{$else cpu64bitalu}
|
||||
if def_cgsize(vardef) in [OS_64,OS_S64] then
|
||||
begin
|
||||
cg.a_reg_sync(list,localloc.register64.reglo);
|
||||
cg.a_reg_sync(list,localloc.register64.reghi);
|
||||
end
|
||||
else
|
||||
{$endif not cpu64bitalu}
|
||||
{$endif cpu64bitalu}
|
||||
cg.a_reg_sync(list,localloc.register);
|
||||
LOC_CFPUREGISTER,
|
||||
LOC_CMMREGISTER:
|
||||
|
||||
@ -1987,6 +1987,7 @@ end;
|
||||
procedure create_codegen;
|
||||
begin
|
||||
cg := tcgppc.create;
|
||||
cg128:=tcg128.create;
|
||||
end;
|
||||
|
||||
end.
|
||||
|
||||
@ -363,6 +363,7 @@ unit cgcpu;
|
||||
procedure create_codegen;
|
||||
begin
|
||||
cg:=tcgx86_64.create;
|
||||
cg128:=tcg128.create;
|
||||
end;
|
||||
|
||||
end.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user