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* moved ncgutil.maybechangeloadnodereg() to hlcg.maybe_change_load_node_reg()
and moved ifdef'd jvm code to overridden method git-svn-id: trunk@27153 -
This commit is contained in:
Jonas Maebe
parent
dab8754bb6
commit
73a3f5ced4
@ -37,12 +37,22 @@ unit hlcgobj;
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cclasses,globtype,constexp,
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cpubase,cgbase,cgutils,parabase,
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aasmbase,aasmtai,aasmdata,aasmcpu,
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symconst,symtype,symdef,
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node
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symconst,symtype,symsym,symdef,
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node,nutils
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;
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type
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tsubsetloadopt = (SL_REG,SL_REGNOSRCMASK,SL_SETZERO,SL_SETMAX);
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preplaceregrec = ^treplaceregrec;
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treplaceregrec = record
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old, new: tregister;
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oldhi, newhi: tregister;
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ressym: tsym;
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{ moved sym }
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sym : tabstractnormalvarsym;
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end;
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{# @abstract(Abstract high level code generator)
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This class implements an abstract instruction generator. All
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methods of this class are generic and are mapped to low level code
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@ -477,6 +487,13 @@ unit hlcgobj;
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procedure location_get_data_ref(list:TAsmList;def: tdef; const l:tlocation;var ref:treference;loadref:boolean; alignment: longint);virtual;
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procedure maketojumpbool(list:TAsmList; p : tnode);virtual;
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{ if the result of n is a LOC_C(..)REGISTER, try to find the corresponding
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loadn and change its location to a new register (= SSA). In case reload
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is true, transfer the old to the new register }
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procedure maybe_change_load_node_reg(list: TAsmList; var n: tnode; reload: boolean); virtual;
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private
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function do_replace_node_regs(var n: tnode; para: pointer): foreachnoderesult; virtual;
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public
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procedure gen_proc_symbol(list:TAsmList);virtual;
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procedure gen_proc_symbol_end(list:TAsmList);virtual;
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@ -555,9 +572,12 @@ implementation
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globals,systems,
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fmodule,export,
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verbose,defutil,paramgr,
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symbase,symsym,symtable,
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ncon,nld,ncgrtti,pass_1,pass_2,
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symbase,symtable,
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nbas,ncon,nld,ncgrtti,pass_1,pass_2,
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cpuinfo,cgobj,tgobj,cutils,procinfo,
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{$ifdef x86}
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cgx86,
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{$endif x86}
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ncgutil,ngenutil;
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@ -3863,6 +3883,225 @@ implementation
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end;
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procedure thlcgobj.maybe_change_load_node_reg(list: TAsmList; var n: tnode; reload: boolean);
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var
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rr: treplaceregrec;
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varloc : tai_varloc;
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begin
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if not (n.location.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMXREGISTER,LOC_CMMREGISTER]) or
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([fc_inflowcontrol,fc_gotolabel,fc_lefthandled] * flowcontrol <> []) then
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exit;
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rr.old := n.location.register;
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rr.ressym := nil;
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rr.sym := nil;
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rr.oldhi := NR_NO;
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case n.location.loc of
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LOC_CREGISTER:
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begin
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{$ifdef cpu64bitalu}
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if (n.location.size in [OS_128,OS_S128]) then
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begin
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rr.oldhi := n.location.register128.reghi;
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rr.new := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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rr.newhi := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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end
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else
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{$else cpu64bitalu}
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if (n.location.size in [OS_64,OS_S64]) then
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begin
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rr.oldhi := n.location.register64.reghi;
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rr.new := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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rr.newhi := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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end
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else
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{$endif cpu64bitalu}
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rr.new := cg.getintregister(current_asmdata.CurrAsmList,n.location.size);
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end;
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LOC_CFPUREGISTER:
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rr.new := cg.getfpuregister(current_asmdata.CurrAsmList,n.location.size);
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{$ifdef SUPPORT_MMX}
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LOC_CMMXREGISTER:
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rr.new := tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
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{$endif SUPPORT_MMX}
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LOC_CMMREGISTER:
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rr.new := cg.getmmregister(current_asmdata.CurrAsmList,n.location.size);
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else
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exit;
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end;
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{ self is implicitly returned from constructors, even if there are no
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references to it; additionally, funcretsym is not set for constructor
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procdefs }
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if (current_procinfo.procdef.proctypeoption=potype_constructor) then
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rr.ressym:=tsym(current_procinfo.procdef.parast.Find('self'))
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else if not is_void(current_procinfo.procdef.returndef) and
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assigned(current_procinfo.procdef.funcretsym) and
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(tabstractvarsym(current_procinfo.procdef.funcretsym).refs <> 0) then
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rr.ressym:=current_procinfo.procdef.funcretsym;
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if not foreachnode(n,@do_replace_node_regs,@rr) then
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exit;
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if reload then
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case n.location.loc of
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LOC_CREGISTER:
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begin
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{$ifdef cpu64bitalu}
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if (n.location.size in [OS_128,OS_S128]) then
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cg128.a_load128_reg_reg(list,n.location.register128,joinreg128(rr.new,rr.newhi))
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else
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{$else cpu64bitalu}
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if (n.location.size in [OS_64,OS_S64]) then
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cg64.a_load64_reg_reg(list,n.location.register64,joinreg64(rr.new,rr.newhi))
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else
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{$endif cpu64bitalu}
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cg.a_load_reg_reg(list,n.location.size,n.location.size,n.location.register,rr.new);
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end;
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LOC_CFPUREGISTER:
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cg.a_loadfpu_reg_reg(list,n.location.size,n.location.size,n.location.register,rr.new);
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{$ifdef SUPPORT_MMX}
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LOC_CMMXREGISTER:
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cg.a_loadmm_reg_reg(list,OS_M64,OS_M64,n.location.register,rr.new,nil);
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{$endif SUPPORT_MMX}
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LOC_CMMREGISTER:
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cg.a_loadmm_reg_reg(list,n.location.size,n.location.size,n.location.register,rr.new,nil);
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else
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internalerror(2006090920);
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end;
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{ now that we've change the loadn/temp, also change the node result location }
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{$ifdef cpu64bitalu}
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if (n.location.size in [OS_128,OS_S128]) then
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begin
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n.location.register128.reglo := rr.new;
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n.location.register128.reghi := rr.newhi;
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if assigned(rr.sym) and
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((rr.sym.currentregloc.register<>rr.new) or
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(rr.sym.currentregloc.registerhi<>rr.newhi)) then
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begin
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varloc:=tai_varloc.create128(rr.sym,rr.new,rr.newhi);
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varloc.oldlocation:=rr.sym.currentregloc.register;
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varloc.oldlocationhi:=rr.sym.currentregloc.registerhi;
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rr.sym.currentregloc.register:=rr.new;
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rr.sym.currentregloc.registerHI:=rr.newhi;
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list.concat(varloc);
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end;
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end
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else
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{$else cpu64bitalu}
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if (n.location.size in [OS_64,OS_S64]) then
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begin
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n.location.register64.reglo := rr.new;
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n.location.register64.reghi := rr.newhi;
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if assigned(rr.sym) and
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((rr.sym.currentregloc.register<>rr.new) or
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(rr.sym.currentregloc.registerhi<>rr.newhi)) then
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begin
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varloc:=tai_varloc.create64(rr.sym,rr.new,rr.newhi);
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varloc.oldlocation:=rr.sym.currentregloc.register;
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varloc.oldlocationhi:=rr.sym.currentregloc.registerhi;
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rr.sym.currentregloc.register:=rr.new;
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rr.sym.currentregloc.registerHI:=rr.newhi;
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list.concat(varloc);
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end;
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end
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else
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{$endif cpu64bitalu}
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begin
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n.location.register := rr.new;
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if assigned(rr.sym) and (rr.sym.currentregloc.register<>rr.new) then
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begin
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varloc:=tai_varloc.create(rr.sym,rr.new);
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varloc.oldlocation:=rr.sym.currentregloc.register;
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rr.sym.currentregloc.register:=rr.new;
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list.concat(varloc);
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end;
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end;
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end;
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function thlcgobj.do_replace_node_regs(var n: tnode; para: pointer): foreachnoderesult;
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var
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rr: preplaceregrec absolute para;
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begin
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result := fen_false;
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if (nf_is_funcret in n.flags) and (fc_exit in flowcontrol) then
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exit;
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case n.nodetype of
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loadn:
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begin
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if (tloadnode(n).symtableentry.typ in [localvarsym,paravarsym,staticvarsym]) and
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(tabstractvarsym(tloadnode(n).symtableentry).varoptions * [vo_is_dll_var, vo_is_thread_var] = []) and
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not assigned(tloadnode(n).left) and
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((tloadnode(n).symtableentry <> rr^.ressym) or
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not(fc_exit in flowcontrol)
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) and
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(tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMXREGISTER,LOC_CMMREGISTER]) and
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(tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register = rr^.old) then
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begin
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{$ifdef cpu64bitalu}
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{ it's possible a 128 bit location was shifted and/xor typecasted }
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{ in a 64 bit value, so only 1 register was left in the location }
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if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.size in [OS_128,OS_S128]) then
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if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register128.reghi = rr^.oldhi) then
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tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register128.reghi := rr^.newhi
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else
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exit;
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{$else cpu64bitalu}
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{ it's possible a 64 bit location was shifted and/xor typecasted }
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{ in a 32 bit value, so only 1 register was left in the location }
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if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.size in [OS_64,OS_S64]) then
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if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register64.reghi = rr^.oldhi) then
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tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register64.reghi := rr^.newhi
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else
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exit;
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{$endif cpu64bitalu}
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tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register := rr^.new;
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rr^.sym := tabstractnormalvarsym(tloadnode(n).symtableentry);
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result := fen_norecurse_true;
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end;
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end;
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temprefn:
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begin
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if (ti_valid in ttemprefnode(n).tempinfo^.flags) and
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(ttemprefnode(n).tempinfo^.location.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMXREGISTER,LOC_CMMREGISTER]) and
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(ttemprefnode(n).tempinfo^.location.register = rr^.old) then
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begin
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{$ifdef cpu64bitalu}
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{ it's possible a 128 bit location was shifted and/xor typecasted }
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{ in a 64 bit value, so only 1 register was left in the location }
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if (ttemprefnode(n).tempinfo^.location.size in [OS_128,OS_S128]) then
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if (ttemprefnode(n).tempinfo^.location.register128.reghi = rr^.oldhi) then
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ttemprefnode(n).tempinfo^.location.register128.reghi := rr^.newhi
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else
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exit;
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{$else cpu64bitalu}
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{ it's possible a 64 bit location was shifted and/xor typecasted }
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{ in a 32 bit value, so only 1 register was left in the location }
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if (ttemprefnode(n).tempinfo^.location.size in [OS_64,OS_S64]) then
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if (ttemprefnode(n).tempinfo^.location.register64.reghi = rr^.oldhi) then
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ttemprefnode(n).tempinfo^.location.register64.reghi := rr^.newhi
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else
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exit;
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{$endif cpu64bitalu}
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ttemprefnode(n).tempinfo^.location.register := rr^.new;
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result := fen_norecurse_true;
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end;
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end;
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{ optimize the searching a bit }
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derefn,addrn,
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calln,inlinen,casen,
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addn,subn,muln,
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andn,orn,xorn,
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ltn,lten,gtn,gten,equaln,unequaln,
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slashn,divn,shrn,shln,notn,
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inn,
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asn,isn:
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result := fen_norecurse_false;
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end;
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end;
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procedure thlcgobj.gen_proc_symbol(list: TAsmList);
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var
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item,
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@ -111,7 +111,7 @@ implementation
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LOC_CREGISTER,
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LOC_REGISTER:
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begin
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maybechangeloadnodereg(current_asmdata.CurrAsmList,left,true);
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hlcg.maybe_change_load_node_reg(current_asmdata.CurrAsmList,left,true);
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location.reference.base := left.location.register;
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location.reference.segment := GetNextReg(left.location.register);
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end;
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@ -30,6 +30,7 @@ uses
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globtype,
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aasmbase,aasmdata,
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symbase,symconst,symtype,symdef,symsym,
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node,
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cpubase, hlcgobj, cgbase, cgutils, parabase;
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type
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@ -103,6 +104,7 @@ uses
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procedure g_overflowCheck_loc(List:TAsmList;const Loc:TLocation;def:TDef;var ovloc : tlocation); override;
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procedure location_get_data_ref(list:TAsmList;def: tdef; const l:tlocation;var ref:treference;loadref:boolean; alignment: longint);override;
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procedure maybe_change_load_node_reg(list: TAsmList; var n: tnode; reload: boolean); override;
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procedure g_copyvaluepara_openarray(list: TAsmList; const ref: treference; const lenloc: tlocation; arrdef: tarraydef; destreg: tregister); override;
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procedure g_releasevaluepara_openarray(list: TAsmList; arrdef: tarraydef; const l: tlocation); override;
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@ -1814,6 +1816,11 @@ implementation
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end;
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end;
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procedure thlcgjvm.maybe_change_load_node_reg(list: TAsmList; var n: tnode; reload: boolean);
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begin
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{ don't do anything, all registers become stack locations anyway }
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end;
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procedure thlcgjvm.g_copyvaluepara_openarray(list: TAsmList; const ref: treference; const lenloc: tlocation; arrdef: tarraydef; destreg: tregister);
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var
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localref: treference;
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@ -263,7 +263,7 @@ implementation
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secondpass(fparainit);
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secondpass(left);
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maybechangeloadnodereg(current_asmdata.CurrAsmList,left,true);
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hlcg.maybe_change_load_node_reg(current_asmdata.CurrAsmList,left,true);
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{ release memory for refcnt out parameters }
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if (parasym.varspez=vs_out) and
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@ -508,7 +508,7 @@ implementation
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current_procinfo.CurrFalseLabel:=ofl;
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end;
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maybechangeloadnodereg(current_asmdata.CurrAsmList,left,false);
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hlcg.maybe_change_load_node_reg(current_asmdata.CurrAsmList,left,false);
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oldflowcontrol:=flowcontrol;
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include(flowcontrol,fc_inflowcontrol);
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{ produce start assignment }
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@ -750,8 +750,8 @@ implementation
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else
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begin
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{ SSA support }
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maybechangeloadnodereg(current_asmdata.CurrAsmList,left,false);
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maybechangeloadnodereg(current_asmdata.CurrAsmList,right,true);
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hlcg.maybe_change_load_node_reg(current_asmdata.CurrAsmList,left,false);
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hlcg.maybe_change_load_node_reg(current_asmdata.CurrAsmList,right,true);
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case right.location.loc of
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LOC_CONSTANT :
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begin
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@ -258,7 +258,7 @@ implementation
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LOC_CREGISTER,
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LOC_REGISTER:
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begin
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maybechangeloadnodereg(current_asmdata.CurrAsmList,left,true);
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hlcg.maybe_change_load_node_reg(current_asmdata.CurrAsmList,left,true);
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{$ifdef cpu_uses_separate_address_registers}
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if getregtype(left.location.register)<>R_ADDRESSREGISTER then
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begin
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@ -97,11 +97,6 @@ interface
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// procedure get_used_regvars_common(n: tnode; var rv: tusedregvarscommon);
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procedure gen_sync_regvars(list:TAsmList; var rv: tusedregvars);
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{ if the result of n is a LOC_C(..)REGISTER, try to find the corresponding
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loadn and change its location to a new register (= SSA). In case reload
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is true, transfer the old to the new register }
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procedure maybechangeloadnodereg(list: TAsmList; var n: tnode; reload: boolean);
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{ Allocate the buffers for exception management and setjmp environment.
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Return a pointer to these buffers, send them to the utility routine
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so they are registered, and then call setjmp.
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@ -571,12 +566,12 @@ implementation
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end
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else
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{$endif cpu64bitalu}
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{ Note: for withs of records (and maybe objects, classes, etc.) an
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{ Note: for widths of records (and maybe objects, classes, etc.) an
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address register could be set here, but that is later
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changed to an intregister neverthless when in the
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tcgassignmentnode maybechangeloadnodereg is called for the
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temporary node; so the workaround for now is to fix the
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symptoms... }
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tcgassignmentnode thlcgobj.maybe_change_load_node_reg is
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called for the temporary node; so the workaround for now is
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to fix the symptoms... }
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l.register:=cg.getintregister(list,l.size);
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end;
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end;
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@ -1789,243 +1784,6 @@ implementation
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end;
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{*****************************************************************************
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SSA support
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*****************************************************************************}
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type
|
||||
preplaceregrec = ^treplaceregrec;
|
||||
treplaceregrec = record
|
||||
old, new: tregister;
|
||||
oldhi, newhi: tregister;
|
||||
ressym: tsym;
|
||||
{ moved sym }
|
||||
sym : tabstractnormalvarsym;
|
||||
end;
|
||||
|
||||
|
||||
function doreplace(var n: tnode; para: pointer): foreachnoderesult;
|
||||
var
|
||||
rr: preplaceregrec absolute para;
|
||||
begin
|
||||
result := fen_false;
|
||||
if (nf_is_funcret in n.flags) and (fc_exit in flowcontrol) then
|
||||
exit;
|
||||
case n.nodetype of
|
||||
loadn:
|
||||
begin
|
||||
if (tloadnode(n).symtableentry.typ in [localvarsym,paravarsym,staticvarsym]) and
|
||||
(tabstractvarsym(tloadnode(n).symtableentry).varoptions * [vo_is_dll_var, vo_is_thread_var] = []) and
|
||||
not assigned(tloadnode(n).left) and
|
||||
((tloadnode(n).symtableentry <> rr^.ressym) or
|
||||
not(fc_exit in flowcontrol)
|
||||
) and
|
||||
(tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMXREGISTER,LOC_CMMREGISTER]) and
|
||||
(tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register = rr^.old) then
|
||||
begin
|
||||
{$ifdef cpu64bitalu}
|
||||
{ it's possible a 128 bit location was shifted and/xor typecasted }
|
||||
{ in a 64 bit value, so only 1 register was left in the location }
|
||||
if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.size in [OS_128,OS_S128]) then
|
||||
if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register128.reghi = rr^.oldhi) then
|
||||
tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register128.reghi := rr^.newhi
|
||||
else
|
||||
exit;
|
||||
{$else cpu64bitalu}
|
||||
{ it's possible a 64 bit location was shifted and/xor typecasted }
|
||||
{ in a 32 bit value, so only 1 register was left in the location }
|
||||
if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.size in [OS_64,OS_S64]) then
|
||||
if (tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register64.reghi = rr^.oldhi) then
|
||||
tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register64.reghi := rr^.newhi
|
||||
else
|
||||
exit;
|
||||
{$endif cpu64bitalu}
|
||||
tabstractnormalvarsym(tloadnode(n).symtableentry).localloc.register := rr^.new;
|
||||
rr^.sym := tabstractnormalvarsym(tloadnode(n).symtableentry);
|
||||
result := fen_norecurse_true;
|
||||
end;
|
||||
end;
|
||||
temprefn:
|
||||
begin
|
||||
if (ti_valid in ttemprefnode(n).tempinfo^.flags) and
|
||||
(ttemprefnode(n).tempinfo^.location.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMXREGISTER,LOC_CMMREGISTER]) and
|
||||
(ttemprefnode(n).tempinfo^.location.register = rr^.old) then
|
||||
begin
|
||||
{$ifdef cpu64bitalu}
|
||||
{ it's possible a 128 bit location was shifted and/xor typecasted }
|
||||
{ in a 64 bit value, so only 1 register was left in the location }
|
||||
if (ttemprefnode(n).tempinfo^.location.size in [OS_128,OS_S128]) then
|
||||
if (ttemprefnode(n).tempinfo^.location.register128.reghi = rr^.oldhi) then
|
||||
ttemprefnode(n).tempinfo^.location.register128.reghi := rr^.newhi
|
||||
else
|
||||
exit;
|
||||
{$else cpu64bitalu}
|
||||
{ it's possible a 64 bit location was shifted and/xor typecasted }
|
||||
{ in a 32 bit value, so only 1 register was left in the location }
|
||||
if (ttemprefnode(n).tempinfo^.location.size in [OS_64,OS_S64]) then
|
||||
if (ttemprefnode(n).tempinfo^.location.register64.reghi = rr^.oldhi) then
|
||||
ttemprefnode(n).tempinfo^.location.register64.reghi := rr^.newhi
|
||||
else
|
||||
exit;
|
||||
{$endif cpu64bitalu}
|
||||
ttemprefnode(n).tempinfo^.location.register := rr^.new;
|
||||
result := fen_norecurse_true;
|
||||
end;
|
||||
end;
|
||||
{ optimize the searching a bit }
|
||||
derefn,addrn,
|
||||
calln,inlinen,casen,
|
||||
addn,subn,muln,
|
||||
andn,orn,xorn,
|
||||
ltn,lten,gtn,gten,equaln,unequaln,
|
||||
slashn,divn,shrn,shln,notn,
|
||||
inn,
|
||||
asn,isn:
|
||||
result := fen_norecurse_false;
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
procedure maybechangeloadnodereg(list: TAsmList; var n: tnode; reload: boolean);
|
||||
var
|
||||
rr: treplaceregrec;
|
||||
varloc : tai_varloc;
|
||||
begin
|
||||
{$ifdef jvm}
|
||||
exit;
|
||||
{$endif}
|
||||
if not (n.location.loc in [LOC_CREGISTER,LOC_CFPUREGISTER,LOC_CMMXREGISTER,LOC_CMMREGISTER]) or
|
||||
([fc_inflowcontrol,fc_gotolabel,fc_lefthandled] * flowcontrol <> []) then
|
||||
exit;
|
||||
rr.old := n.location.register;
|
||||
rr.ressym := nil;
|
||||
rr.sym := nil;
|
||||
rr.oldhi := NR_NO;
|
||||
case n.location.loc of
|
||||
LOC_CREGISTER:
|
||||
begin
|
||||
{$ifdef cpu64bitalu}
|
||||
if (n.location.size in [OS_128,OS_S128]) then
|
||||
begin
|
||||
rr.oldhi := n.location.register128.reghi;
|
||||
rr.new := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
||||
rr.newhi := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
||||
end
|
||||
else
|
||||
{$else cpu64bitalu}
|
||||
if (n.location.size in [OS_64,OS_S64]) then
|
||||
begin
|
||||
rr.oldhi := n.location.register64.reghi;
|
||||
rr.new := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
||||
rr.newhi := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
||||
end
|
||||
else
|
||||
{$endif cpu64bitalu}
|
||||
rr.new := cg.getintregister(current_asmdata.CurrAsmList,n.location.size);
|
||||
end;
|
||||
LOC_CFPUREGISTER:
|
||||
rr.new := cg.getfpuregister(current_asmdata.CurrAsmList,n.location.size);
|
||||
{$ifdef SUPPORT_MMX}
|
||||
LOC_CMMXREGISTER:
|
||||
rr.new := tcgx86(cg).getmmxregister(current_asmdata.CurrAsmList);
|
||||
{$endif SUPPORT_MMX}
|
||||
LOC_CMMREGISTER:
|
||||
rr.new := cg.getmmregister(current_asmdata.CurrAsmList,n.location.size);
|
||||
else
|
||||
exit;
|
||||
end;
|
||||
|
||||
{ self is implicitly returned from constructors, even if there are no
|
||||
references to it; additionally, funcretsym is not set for constructor
|
||||
procdefs }
|
||||
if (current_procinfo.procdef.proctypeoption=potype_constructor) then
|
||||
rr.ressym:=tsym(current_procinfo.procdef.parast.Find('self'))
|
||||
else if not is_void(current_procinfo.procdef.returndef) and
|
||||
assigned(current_procinfo.procdef.funcretsym) and
|
||||
(tabstractvarsym(current_procinfo.procdef.funcretsym).refs <> 0) then
|
||||
rr.ressym:=current_procinfo.procdef.funcretsym;
|
||||
|
||||
if not foreachnodestatic(n,@doreplace,@rr) then
|
||||
exit;
|
||||
|
||||
if reload then
|
||||
case n.location.loc of
|
||||
LOC_CREGISTER:
|
||||
begin
|
||||
{$ifdef cpu64bitalu}
|
||||
if (n.location.size in [OS_128,OS_S128]) then
|
||||
cg128.a_load128_reg_reg(list,n.location.register128,joinreg128(rr.new,rr.newhi))
|
||||
else
|
||||
{$else cpu64bitalu}
|
||||
if (n.location.size in [OS_64,OS_S64]) then
|
||||
cg64.a_load64_reg_reg(list,n.location.register64,joinreg64(rr.new,rr.newhi))
|
||||
else
|
||||
{$endif cpu64bitalu}
|
||||
cg.a_load_reg_reg(list,n.location.size,n.location.size,n.location.register,rr.new);
|
||||
end;
|
||||
LOC_CFPUREGISTER:
|
||||
cg.a_loadfpu_reg_reg(list,n.location.size,n.location.size,n.location.register,rr.new);
|
||||
{$ifdef SUPPORT_MMX}
|
||||
LOC_CMMXREGISTER:
|
||||
cg.a_loadmm_reg_reg(list,OS_M64,OS_M64,n.location.register,rr.new,nil);
|
||||
{$endif SUPPORT_MMX}
|
||||
LOC_CMMREGISTER:
|
||||
cg.a_loadmm_reg_reg(list,n.location.size,n.location.size,n.location.register,rr.new,nil);
|
||||
else
|
||||
internalerror(2006090920);
|
||||
end;
|
||||
|
||||
{ now that we've change the loadn/temp, also change the node result location }
|
||||
{$ifdef cpu64bitalu}
|
||||
if (n.location.size in [OS_128,OS_S128]) then
|
||||
begin
|
||||
n.location.register128.reglo := rr.new;
|
||||
n.location.register128.reghi := rr.newhi;
|
||||
if assigned(rr.sym) and
|
||||
((rr.sym.currentregloc.register<>rr.new) or
|
||||
(rr.sym.currentregloc.registerhi<>rr.newhi)) then
|
||||
begin
|
||||
varloc:=tai_varloc.create128(rr.sym,rr.new,rr.newhi);
|
||||
varloc.oldlocation:=rr.sym.currentregloc.register;
|
||||
varloc.oldlocationhi:=rr.sym.currentregloc.registerhi;
|
||||
rr.sym.currentregloc.register:=rr.new;
|
||||
rr.sym.currentregloc.registerHI:=rr.newhi;
|
||||
list.concat(varloc);
|
||||
end;
|
||||
end
|
||||
else
|
||||
{$else cpu64bitalu}
|
||||
if (n.location.size in [OS_64,OS_S64]) then
|
||||
begin
|
||||
n.location.register64.reglo := rr.new;
|
||||
n.location.register64.reghi := rr.newhi;
|
||||
if assigned(rr.sym) and
|
||||
((rr.sym.currentregloc.register<>rr.new) or
|
||||
(rr.sym.currentregloc.registerhi<>rr.newhi)) then
|
||||
begin
|
||||
varloc:=tai_varloc.create64(rr.sym,rr.new,rr.newhi);
|
||||
varloc.oldlocation:=rr.sym.currentregloc.register;
|
||||
varloc.oldlocationhi:=rr.sym.currentregloc.registerhi;
|
||||
rr.sym.currentregloc.register:=rr.new;
|
||||
rr.sym.currentregloc.registerHI:=rr.newhi;
|
||||
list.concat(varloc);
|
||||
end;
|
||||
end
|
||||
else
|
||||
{$endif cpu64bitalu}
|
||||
begin
|
||||
n.location.register := rr.new;
|
||||
if assigned(rr.sym) and (rr.sym.currentregloc.register<>rr.new) then
|
||||
begin
|
||||
varloc:=tai_varloc.create(rr.sym,rr.new);
|
||||
varloc.oldlocation:=rr.sym.currentregloc.register;
|
||||
rr.sym.currentregloc.register:=rr.new;
|
||||
list.concat(varloc);
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
procedure gen_free_symtable(list:TAsmList;st:TSymtable);
|
||||
var
|
||||
i : longint;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user