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+ cpu flag CPUARM_HAS_THUMB_IDIV

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* test for CPUARM_HAS_THUMB_IDIV instead the CPU type when creating sdiv/udiv code

git-svn-id: trunk@25648 -
This commit is contained in:
florian 2013-10-05 12:38:55 +00:00
parent 8fb7cf822b
commit 73e6af4864
2 changed files with 7 additions and 6 deletions
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7
compiler/arm/cpuinfo.pas
View File

@ -663,6 +663,7 @@ Const
CPUARM_HAS_DMB, { CPU has memory barrier instructions (DMB, DSB, ISB) }
CPUARM_HAS_LDREX,
CPUARM_HAS_IDIV,
CPUARM_HAS_THUMB_IDIV,
CPUARM_HAS_THUMB2
);
@ -684,9 +685,9 @@ Const
{ the identifier armv7 is should not be used, it is considered being equal to armv7a }
{ cpu_armv7 } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2],
{ cpu_armv7a } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2],
{ cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2],
{ cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2],
{ cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2]
{ cpu_armv7r } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_BLX_LABEL,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_THUMB_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2],
{ cpu_armv7m } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_THUMB_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2],
{ cpu_armv7em } [CPUARM_HAS_BX,CPUARM_HAS_BLX,CPUARM_HAS_CLZ,CPUARM_HAS_EDSP,CPUARM_HAS_REV,CPUARM_HAS_RBIT,CPUARM_HAS_LDREX,CPUARM_HAS_THUMB_IDIV,CPUARM_HAS_DMB,CPUARM_HAS_THUMB2]
);
{ contains all CPU supporting any kind of thumb instruction set }

6
compiler/arm/narmmat.pas
View File

@ -79,11 +79,11 @@ implementation
) and
not(is_64bitint(resultdef)) then
result:=nil
else if (current_settings.cputype in [cpu_armv7m,cpu_armv7em]) and
else if ((GenerateThumbCode) and (CPUARM_HAS_THUMB_IDIV in cpu_capabilities[current_settings.cputype])) and
(nodetype=divn) and
not(is_64bitint(resultdef)) then
result:=nil
else if (current_settings.cputype in [cpu_armv7m,cpu_armv7em]) and
else if ((GenerateThumbCode) and (CPUARM_HAS_THUMB_IDIV in cpu_capabilities[current_settings.cputype])) and
(nodetype=modn) and
not(is_64bitint(resultdef)) then
begin
@ -220,7 +220,7 @@ implementation
secondpass(left);
secondpass(right);
if (current_settings.cputype in [cpu_armv7m,cpu_armv7em]) and
if ((GenerateThumbCode) and (CPUARM_HAS_THUMB_IDIV in cpu_capabilities[current_settings.cputype])) and
(nodetype=divn) and
not(is_64bitint(resultdef)) then
begin