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* fix and enable MovOpMov2MovOp optimization on x86-64

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git-svn-id: trunk@40941 -
This commit is contained in:
florian 2019-01-20 17:00:43 +00:00
parent 80e014d94a
commit 75a89d2115
1 changed files with 5 additions and 4 deletions
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9
compiler/x86/aoptx86.pas
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@ -1840,9 +1840,12 @@ unit aoptx86;
p := hp1;
end;
end
{$ifndef x86_64}
else if MatchOpType(taicpu(hp2),top_reg,top_reg) and
not(SuperRegistersEqual(taicpu(hp1).oper[0]^.reg,taicpu(hp2).oper[1]^.reg))
not(SuperRegistersEqual(taicpu(hp1).oper[0]^.reg,taicpu(hp2).oper[1]^.reg)) and
(not((taicpu(hp1).opsize=S_Q) and (taicpu(hp2).opsize=S_L)) or
{ opsize matters for these opcodes, we could probably work around this, but it is not worth the effort }
((taicpu(hp1).opcode<>A_SHL) and (taicpu(hp1).opcode<>A_SHR) and (taicpu(hp1).opcode<>A_SAR))
)
{$ifdef i386}
{ byte registers of esi, edi, ebp, esp are not available on i386 }
and ((taicpu(hp2).opsize<>S_B) or not(getsupreg(taicpu(hp1).oper[0]^.reg) in [RS_ESI,RS_EDI,RS_EBP,RS_ESP]))
@ -1913,10 +1916,8 @@ unit aoptx86;
}
asml.remove(hp2);
hp2.Free;
// p := hp1;
end;
end;
{$endif x86_64}
end
else if GetNextInstruction_p and
MatchInstruction(hp1,A_BTS,A_BTR,[Taicpu(p).opsize]) and