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* x86: Convert isolated "(1 shl y) - 1" to BZHI, not just "x and ((1 shl y) - 1)"
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
1d5a31ed41
commit
79eee75aa0
@ -1903,7 +1903,37 @@ unit nx86add;
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ovloc : tlocation;
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tmpreg : TRegister;
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indexnode : TNode;
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procedure MakeBZHI(use_tmpreg: Boolean);
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begin
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{ allocate registers }
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hlcg.location_force_reg(
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current_asmdata.CurrAsmList,
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indexnode.location,
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indexnode.resultdef,
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resultdef,
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false
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);
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set_result_location_reg;
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if use_tmpreg then
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emit_reg_reg_reg(A_BZHI, TCGSize2OpSize[opsize], indexnode.location.register, tmpreg, location.register)
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else
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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emit_reg_ref_reg(A_BZHI, TCGSize2OpSize[opsize], indexnode.location.register, left.location.reference, location.register);
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LOC_REGISTER,
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LOC_CREGISTER:
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emit_reg_reg_reg(A_BZHI, TCGSize2OpSize[opsize], indexnode.location.register, left.location.register, location.register);
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else
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InternalError(2022102111);
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end;
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end;
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begin
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indexnode := nil; { Needed to prevent a compiler warning }
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{ determine if the comparison will be unsigned }
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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@ -2029,86 +2059,109 @@ unit nx86add;
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end;
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{ BMI2 optimisations }
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if (CPUX86_HAS_BMI2 in cpu_capabilities[current_settings.cputype]) then
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if (CPUX86_HAS_BMI2 in cpu_capabilities[current_settings.cputype]) and
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(opsize in [OS_32, OS_S32{$ifdef x86_64}, OS_64, OS_S64{$endif x86_64}]) then
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begin
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{ Can we turn "x and ((1 shl y) - 1)" into a BZHI instruction instead? }
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if (nodetype = andn) and
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(opsize in [OS_32, OS_S32{$ifdef x86_64}, OS_64, OS_S64{$endif x86_64}]) and
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(
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(
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(right.nodetype = subn) and
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(taddnode(right).right.nodetype = ordconstn) and
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(tordconstnode(taddnode(right).right).value = 1) and
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(taddnode(right).left.nodetype = shln) and
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(tshlshrnode(taddnode(right).left).left.nodetype = ordconstn) and
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(tordconstnode(tshlshrnode(taddnode(right).left).left).value = 1)
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) or
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(
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(left.nodetype = subn) and
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(taddnode(left).right.nodetype = ordconstn) and
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(tordconstnode(taddnode(left).right).value = 1) and
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(taddnode(left).left.nodetype = shln) and
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(tshlshrnode(taddnode(left).left).left.nodetype = ordconstn) and
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(tordconstnode(tshlshrnode(taddnode(left).left).left).value = 1)
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)
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) then
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begin
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{ Put the subtract node on the right }
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if (right.nodetype <> subn) then
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swapleftright;
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secondpass(left);
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{ Skip the subtract and shift nodes completely }
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Include(right.transientflags, tnf_do_not_execute);
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Include(taddnode(right).left.transientflags, tnf_do_not_execute);
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{ Helps avoid all the awkward typecasts }
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indexnode := tshlshrnode(taddnode(right).left).right;
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{$ifdef x86_64}
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{ The code generator sometimes extends the shift result to 64-bit unnecessarily }
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if (indexnode.nodetype = typeconvn) and (opsize in [OS_32, OS_S32]) and
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(def_cgsize(TTypeConvNode(indexnode).resultdef) in [OS_64, OS_S64]) then
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case nodetype of
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andn:
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{ Can we turn "x and ((1 shl y) - 1)" into a BZHI instruction instead? }
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if (
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(
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(right.nodetype = subn) and
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(taddnode(right).right.nodetype = ordconstn) and
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(tordconstnode(taddnode(right).right).value = 1) and
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(taddnode(right).left.nodetype = shln) and
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(tshlshrnode(taddnode(right).left).left.nodetype = ordconstn) and
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(tordconstnode(tshlshrnode(taddnode(right).left).left).value = 1)
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) or
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(
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(left.nodetype = subn) and
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(taddnode(left).right.nodetype = ordconstn) and
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(tordconstnode(taddnode(left).right).value = 1) and
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(taddnode(left).left.nodetype = shln) and
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(tshlshrnode(taddnode(left).left).left.nodetype = ordconstn) and
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(tordconstnode(tshlshrnode(taddnode(left).left).left).value = 1)
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)
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) then
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begin
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{ Convert to the 32-bit type }
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indexnode.resultdef := resultdef;
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node_reset_flags(indexnode,[],[tnf_pass1_done]);
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{ We should't be getting any new errors }
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if do_firstpass(indexnode) then
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InternalError(2022110201);
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{ Put the subtract node on the right }
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if (right.nodetype <> subn) then
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swapleftright;
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{ Keep things internally consistent in case indexnode changed }
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tshlshrnode(taddnode(right).left).right := indexnode;
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end;
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secondpass(left);
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{ Skip the subtract and shift nodes completely }
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Include(right.transientflags, tnf_do_not_execute);
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Include(taddnode(right).left.transientflags, tnf_do_not_execute);
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{ Helps avoid all the awkward typecasts }
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indexnode := tshlshrnode(taddnode(right).left).right;
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{$ifdef x86_64}
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{ The code generator sometimes extends the shift result to 64-bit unnecessarily }
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if (indexnode.nodetype = typeconvn) and (opsize in [OS_32, OS_S32]) and
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(def_cgsize(TTypeConvNode(indexnode).resultdef) in [OS_64, OS_S64]) then
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begin
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{ Convert to the 32-bit type }
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indexnode.resultdef := resultdef;
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node_reset_flags(indexnode,[],[tnf_pass1_done]);
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{ We should't be getting any new errors }
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if do_firstpass(indexnode) then
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InternalError(2022110201);
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{ Keep things internally consistent in case indexnode changed }
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tshlshrnode(taddnode(right).left).right := indexnode;
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end;
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{$endif x86_64}
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secondpass(indexnode);
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secondpass(indexnode);
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{ allocate registers }
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hlcg.location_force_reg(
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current_asmdata.CurrAsmList,
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indexnode.location,
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indexnode.resultdef,
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resultdef,
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false
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);
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MakeBZHI(False);
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Exit;
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end;
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set_result_location_reg;
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subn:
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{ Turns an isolated "(1 shl y) - 1" into "mov $-1,%reg1; bzhi %idxreg,%reg1,%reg2" pair}
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if (right.nodetype = ordconstn) and
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(tordconstnode(right).value = 1) and
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(left.nodetype = shln) and
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(tshlshrnode(left).left.nodetype = ordconstn) and
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(tordconstnode(tshlshrnode(left).left).value = 1) then
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begin
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{ Skip the shift node completely }
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Include(left.transientflags, tnf_do_not_execute);
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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emit_reg_ref_reg(A_BZHI, TCGSize2OpSize[opsize], indexnode.location.register, left.location.reference, location.register);
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LOC_REGISTER,
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LOC_CREGISTER:
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emit_reg_reg_reg(A_BZHI, TCGSize2OpSize[opsize], indexnode.location.register, left.location.register, location.register);
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else
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InternalError(2022102111);
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end;
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{ Helps avoid all the awkward typecasts }
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indexnode := tshlshrnode(left).right;
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Exit;
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end;
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{$ifdef x86_64}
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{ The code generator sometimes extends the shift result to 64-bit unnecessarily }
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if (indexnode.nodetype = typeconvn) and (opsize in [OS_32, OS_S32]) and
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(def_cgsize(ttypeconvnode(indexnode).resultdef) in [OS_64, OS_S64]) then
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begin
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{ Convert to the 32-bit type }
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indexnode.resultdef := resultdef;
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node_reset_flags(indexnode,[],[tnf_pass1_done]);
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{ We should't be getting any new errors }
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if do_firstpass(indexnode) then
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InternalError(2022110202);
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{ Keep things internally consistent in case indexnode changed }
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tshlshrnode(left).right := indexnode;
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end;
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{$endif x86_64}
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secondpass(indexnode);
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tmpreg := cg.getintregister(current_asmdata.CurrAsmList, opsize);
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cg.a_load_const_reg(current_asmdata.CurrAsmList, opsize, -1, tmpreg);
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MakeBZHI(True);
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Exit;
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end;
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else
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;
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end;
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end;
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end;
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{$endif not i8086}
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