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- MIPS,SPARC and ARM-wince: removed remaining references to softfloat stuff.

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git-svn-id: trunk@27204 -
This commit is contained in:
sergei 2014-03-20 17:46:01 +00:00
parent cfd2600b24
commit 7b56c90d82
5 changed files with 0 additions and 65 deletions
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2
rtl/arm/arm.inc
View File

@ -80,13 +80,11 @@ function _controlfp(new: DWORD; mask: DWORD): DWORD; cdecl; external 'coredll';
{$define FPC_SYSTEM_HAS_SYSRESETFPU}
Procedure SysResetFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
begin
softfloat_exception_flags:=0;
end;
{$define FPC_SYSTEM_HAS_SYSINITFPU}
Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
begin
softfloat_exception_mask:=float_flag_underflow or float_flag_inexact or float_flag_denormal;
{ Enable FPU exceptions, but disable INEXACT, UNDERFLOW, DENORMAL }
{ FPU precision 64 bit, rounding to nearest, affine infinity }
_controlfp($000C0003, $030F031F);

11
rtl/arm/mathu.inc
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@ -91,16 +91,6 @@ function SetRoundMode(const RoundMode: TFPURoundingMode): TFPURoundingMode;
var
c: dword;
begin
case (RoundMode) of
rmNearest :
softfloat_rounding_mode := float_round_nearest_even;
rmTruncate :
softfloat_rounding_mode := float_round_to_zero;
rmUp :
softfloat_rounding_mode := float_round_up;
rmDown :
softfloat_rounding_mode := float_round_down;
end;
c:=Ord(RoundMode) shl 16;
c:=_controlfp(c, _MCW_RC);
Result:=TFPURoundingMode((c shr 16) and 3);
@ -170,7 +160,6 @@ begin
c:=c or _EM_INEXACT;
c:=_controlfp(c, _MCW_EM);
Result:=ConvertExceptionMask(c);
softfloat_exception_mask:=FPUExceptionMaskToSoftFloatMask(mask);
end;
procedure ClearExceptions(RaisePending: Boolean =true);

21
rtl/mips/mathu.inc
View File

@ -36,24 +36,6 @@ const
fpu_rounding_plus_inf = 2;
fpu_rounding_minus_inf = 3;
function FPUExceptionMaskToSoftFloatMask(const Mask: TFPUExceptionMask): byte;
begin
result:=0;
if exInvalidOp in Mask then
result:=result or (1 shl ord(exInvalidOp));
if exDenormalized in Mask then
result:=result or (1 shl ord(exDenormalized));
if exZeroDivide in Mask then
result:=result or (1 shl ord(exZeroDivide));
if exOverflow in Mask then
result:=result or (1 shl ord(exOverflow));
if exUnderflow in Mask then
result:=result or (1 shl ord(exUnderflow));
if exPrecision in Mask then
result:=result or (1 shl ord(exPrecision));
end;
const
roundmode2fsr : array [TFPURoundingMode] of byte=(
fpu_rounding_nearest,
@ -78,7 +60,6 @@ function SetRoundMode(const RoundMode: TFPURoundingMode): TFPURoundingMode;
var
fsr: longword;
begin
softfloat_rounding_mode:=byte(RoundMode);
fsr:=get_fsr;
result:=fsr2roundmode[fsr and fpu_rounding_mask];
set_fsr((fsr and not fpu_rounding_mask) or roundmode2fsr[RoundMode]);
@ -160,8 +141,6 @@ function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
{ update control register contents }
set_fsr(fsr);
softfloat_exception_mask:=FPUExceptionMaskToSoftFloatMask(mask);
end;

29
rtl/sparc/mathu.inc
View File

@ -16,23 +16,6 @@
function get_fsr : dword;external name 'FPC_GETFSR';
procedure set_fsr(fsr : dword);external name 'FPC_SETFSR';
function FPUExceptionMaskToSoftFloatMask(const Mask: TFPUExceptionMask): byte;
begin
result:=0;
if exInvalidOp in Mask then
result:=result or (1 shl ord(exInvalidOp));
if exDenormalized in Mask then
result:=result or (1 shl ord(exDenormalized));
if exZeroDivide in Mask then
result:=result or (1 shl ord(exZeroDivide));
if exOverflow in Mask then
result:=result or (1 shl ord(exOverflow));
if exUnderflow in Mask then
result:=result or (1 shl ord(exUnderflow));
if exPrecision in Mask then
result:=result or (1 shl ord(exPrecision));
end;
function GetRoundMode: TFPURoundingMode;
begin
result:=TFPURoundingMode(get_fsr shr 30);
@ -40,16 +23,6 @@ function GetRoundMode: TFPURoundingMode;
function SetRoundMode(const RoundMode: TFPURoundingMode): TFPURoundingMode;
begin
case (RoundMode) of
rmNearest :
softfloat_rounding_mode := float_round_nearest_even;
rmTruncate :
softfloat_rounding_mode := float_round_to_zero;
rmUp :
softfloat_rounding_mode := float_round_up;
rmDown :
softfloat_rounding_mode := float_round_down;
end;
set_fsr((get_fsr and $3fffffff) or (dword(RoundMode) shl 30));
result:=TFPURoundingMode(get_fsr shr 30);
end;
@ -134,8 +107,6 @@ function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
{ update control register contents }
set_fsr(fsr);
softfloat_exception_mask:=FPUExceptionMaskToSoftFloatMask(mask);
end;

2
rtl/sparc/sparc.inc
View File

@ -49,7 +49,6 @@ function get_got : pointer;assembler;nostackframe;[public, alias: 'FPC_GETGOT'];
{$define FPC_SYSTEM_HAS_SYSINITFPU}
Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
begin
softfloat_exception_mask:=float_flag_underflow or float_flag_inexact or float_flag_denormal;
{ enable div by 0 and invalid operation fpu exceptions
round towards zero; ieee compliant arithmetics }
set_fsr((get_fsr and $3fbfffff) or $09000000);
@ -58,7 +57,6 @@ Procedure SysInitFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
{$define FPC_SYSTEM_HAS_SYSRESETFPU}
Procedure SysResetFPU;{$ifdef SYSTEMINLINE}inline;{$endif}
begin
softfloat_exception_flags:=0;
end;