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* x86: The code generator will now attempt to manipulate "x and ((1 shl y) - 1)" to use BZHI
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
e748e4c7ab
commit
7da9b4a988
@ -79,10 +79,10 @@ unit nx86add;
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aasmbase,aasmdata,aasmcpu,
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symconst,symdef,
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cgobj,hlcgobj,cgx86,cga,cgutils,
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tgobj,ncgutil,
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tgobj,ncgutil,nutils,
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ncon,nset,ninl,ncnv,ncal,nmat,
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defutil,defcmp,constexp,
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pass_2,htypechk;
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pass_1,pass_2,htypechk;
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{ Range check must be disabled explicitly as the code serves
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on three different architecture sizes }
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@ -1892,6 +1892,7 @@ unit nx86add;
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checkoverflow : Boolean;
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ovloc : tlocation;
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tmpreg : TRegister;
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indexnode : TNode;
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begin
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{ determine if the comparison will be unsigned }
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unsigned:=not(is_signed(left.resultdef)) or
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@ -1944,73 +1945,156 @@ unit nx86add;
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opsize:=def_cgsize(left.resultdef);
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{$ifndef i8086}
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{ BMI1 optimisations }
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if (cs_opt_level2 in current_settings.optimizerswitches) and
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(CPUX86_HAS_BMI1 in cpu_capabilities[current_settings.cputype]) then
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if (cs_opt_level2 in current_settings.optimizerswitches) then
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begin
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{ Can we turn "x and (not y)" into an ANDN instruction instead? }
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if (nodetype = andn) and
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(opsize in [OS_32, OS_S32{$ifdef x86_64}, OS_64, OS_S64{$endif x86_64}]) and
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((left.nodetype = notn) or (right.nodetype = notn)) and
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(
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{ With "const and (not variable)", ANDN will produce larger
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code once everything is moved into registers (as a side-note,
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"const and (not const)" and "variable and (not const)" will
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have been simplified earlier to remove the NOT operation). }
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not (cs_opt_size in current_settings.optimizerswitches) or
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(
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(left.location.loc <> LOC_CONSTANT) and
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(right.location.loc <> LOC_CONSTANT)
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)
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) then
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{ BMI1 optimisations }
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if (CPUX86_HAS_BMI1 in cpu_capabilities[current_settings.cputype]) then
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begin
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{ ANDN only supports the second operand being inverted; however,
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since we're dealing with ordinals, there won't be any Boolean
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shortcutting, so we can safely swap the parameters }
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{ Can we turn "x and (not y)" into an ANDN instruction instead? }
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if (nodetype = andn) and
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(opsize in [OS_32, OS_S32{$ifdef x86_64}, OS_64, OS_S64{$endif x86_64}]) and
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((left.nodetype = notn) or (right.nodetype = notn)) and
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(
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{ With "const and (not variable)", ANDN will produce larger
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code once everything is moved into registers (as a side-note,
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"const and (not const)" and "variable and (not const)" will
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have been simplified earlier to remove the NOT operation). }
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not (cs_opt_size in current_settings.optimizerswitches) or
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(
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(left.location.loc <> LOC_CONSTANT) and
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(right.location.loc <> LOC_CONSTANT)
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)
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) then
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begin
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{ ANDN only supports the second operand being inverted; however,
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since we're dealing with ordinals, there won't be any Boolean
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shortcutting, so we can safely swap the parameters }
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if (right.nodetype <> notn) then
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swapleftright;
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if (right.nodetype <> notn) then
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swapleftright;
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secondpass(left);
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{ Skip the not node completely }
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secondpass(tnotnode(right).left);
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secondpass(left);
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{ Skip the not node completely }
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secondpass(tnotnode(right).left);
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{ allocate registers }
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hlcg.location_force_reg(
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current_asmdata.CurrAsmList,
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tnotnode(right).left.location,
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tnotnode(right).left.resultdef,
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tnotnode(right).left.resultdef,
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false
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);
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{ allocate registers }
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hlcg.location_force_reg(
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current_asmdata.CurrAsmList,
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tnotnode(right).left.location,
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tnotnode(right).left.resultdef,
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tnotnode(right).left.resultdef,
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false
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);
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if left.location.loc = LOC_CONSTANT then
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{ With "const and (not variable)", we can probably still make a
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saving when it comes to pipeline stalls (left.location.loc
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will become LOC_CREGISTER). }
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hlcg.location_force_reg(
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current_asmdata.CurrAsmList,
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left.location,
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left.resultdef,
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left.resultdef,
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true
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);
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if left.location.loc = LOC_CONSTANT then
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{ With "const and (not variable)", we can probably still make a
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saving when it comes to pipeline stalls (left.location.loc
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will become LOC_CREGISTER). }
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hlcg.location_force_reg(
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current_asmdata.CurrAsmList,
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left.location,
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left.resultdef,
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left.resultdef,
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true
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);
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set_result_location_reg;
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set_result_location_reg;
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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emit_ref_reg_reg(A_ANDN, TCGSize2OpSize[opsize], left.location.reference, tnotnode(right).left.location.register, location.register);
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LOC_REGISTER,
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LOC_CREGISTER:
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emit_reg_reg_reg(A_ANDN, TCGSize2OpSize[opsize], left.location.register, tnotnode(right).left.location.register, location.register)
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else
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InternalError(2022102101);
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end;
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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emit_ref_reg_reg(A_ANDN, TCGSize2OpSize[opsize], left.location.reference, tnotnode(right).left.location.register, location.register);
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LOC_REGISTER,
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LOC_CREGISTER:
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emit_reg_reg_reg(A_ANDN, TCGSize2OpSize[opsize], left.location.register, tnotnode(right).left.location.register, location.register);
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else
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InternalError(2022102110);
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end;
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{ Overflow can't happen with and/andn }
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Exit;
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{ Overflow can't happen with and/andn }
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Exit;
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end;
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end;
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{ BMI2 optimisations }
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if (CPUX86_HAS_BMI2 in cpu_capabilities[current_settings.cputype]) then
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begin
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{ Can we turn "x and ((1 shl y) - 1)" into a BZHI instruction instead? }
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if (nodetype = andn) and
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(opsize in [OS_32, OS_S32{$ifdef x86_64}, OS_64, OS_S64{$endif x86_64}]) and
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(
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(
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(right.nodetype = subn) and
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(taddnode(right).right.nodetype = ordconstn) and
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(tordconstnode(taddnode(right).right).value = 1) and
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(taddnode(right).left.nodetype = shln) and
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(tshlshrnode(taddnode(right).left).left.nodetype = ordconstn) and
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(tordconstnode(tshlshrnode(taddnode(right).left).left).value = 1)
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) or
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(
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(left.nodetype = subn) and
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(taddnode(left).right.nodetype = ordconstn) and
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(tordconstnode(taddnode(left).right).value = 1) and
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(taddnode(left).left.nodetype = shln) and
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(tshlshrnode(taddnode(left).left).left.nodetype = ordconstn) and
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(tordconstnode(tshlshrnode(taddnode(left).left).left).value = 1)
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)
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) then
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begin
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{ Put the subtract node on the right }
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if (right.nodetype <> subn) then
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swapleftright;
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secondpass(left);
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{ Skip the subtract and shift nodes completely }
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{ Helps avoid all the awkward typecasts }
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indexnode := tshlshrnode(taddnode(right).left).right;
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{$ifdef x86_64}
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{ The code generator sometimes extends the shift result to 64-bit unnecessarily }
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if (indexnode.nodetype = typeconvn) and (opsize in [OS_32, OS_S32]) and
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(def_cgsize(TTypeConvNode(indexnode).resultdef) in [OS_64, OS_S64]) then
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begin
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{ Convert to the 32-bit type }
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indexnode.resultdef := resultdef;
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node_reset_flags(indexnode,[nf_pass1_done]);
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{ We should't be getting any new errors }
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if do_firstpass(indexnode) then
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InternalError(2022110201);
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{ Keep things internally consistent in case indexnode changed }
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tshlshrnode(taddnode(right).left).right := indexnode;
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end;
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{$endif x86_64}
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secondpass(indexnode);
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{ allocate registers }
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hlcg.location_force_reg(
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current_asmdata.CurrAsmList,
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indexnode.location,
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indexnode.resultdef,
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resultdef,
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false
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);
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set_result_location_reg;
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case left.location.loc of
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LOC_REFERENCE,
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LOC_CREFERENCE:
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emit_reg_ref_reg(A_BZHI, TCGSize2OpSize[opsize], indexnode.location.register, left.location.reference, location.register);
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LOC_REGISTER,
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LOC_CREGISTER:
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emit_reg_reg_reg(A_BZHI, TCGSize2OpSize[opsize], indexnode.location.register, left.location.register, location.register);
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else
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InternalError(2022102111);
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end;
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Exit;
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end;
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end;
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end;
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{$endif not i8086}
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