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* MIPS: changed function is_macro_instruction into method of taicpu. Functionality unchanged.

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git-svn-id: trunk@33081 -
This commit is contained in:
sergei 2016-02-10 12:46:55 +00:00
parent 5f17bcbc97
commit 7f58608008
2 changed files with 23 additions and 23 deletions
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21
compiler/mips/aasmcpu.pas
View File

@ -70,6 +70,8 @@ type
{ register spilling code }
function spilling_get_operation_type(opnr: longint): topertype; override;
function is_macro: boolean;
end;
tai_align = class(tai_align_abstract)
@ -254,6 +256,25 @@ begin
end;
function taicpu.is_macro: boolean;
begin
result :=
{ 'seq', 'sge', 'sgeu', 'sgt', 'sgtu', 'sle', 'sleu', 'sne', }
(opcode=A_SEQ) or (opcode=A_SGE) or (opcode=A_SGEU) or (opcode=A_SGT) or
(opcode=A_SGTU) or (opcode=A_SLE) or (opcode=A_SLEU) or (opcode=A_SNE)
{ JAL is not here! See comments in TCGMIPS.a_call_name. }
or (opcode=A_LA) or ((opcode=A_BC) and
not (condition in [C_EQ,C_NE,C_GTZ,C_GEZ,C_LTZ,C_LEZ,C_COP1TRUE,C_COP1FALSE])) {or (op=A_JAL)}
or (opcode=A_REM) or (opcode=A_REMU)
{ DIV and DIVU are normally macros, but use $zero as first arg to generate a CPU instruction. }
or (((opcode=A_DIV) or (opcode=A_DIVU)) and
((ops<>3) or (oper[0]^.typ<>top_reg) or (oper[0]^.reg<>NR_R0)))
or (opcode=A_MULO) or (opcode=A_MULOU)
{ A_LI is only a macro if the immediate is not in thez 16-bit range }
or (opcode=A_LI);
end;
function taicpu.spilling_get_operation_type(opnr: longint): topertype;
type
op_write_set_type = set of TAsmOp;

25
compiler/mips/cpugas.pas
View File

@ -211,27 +211,6 @@ unit cpugas;
end;
}
function is_macro_instruction(ai : taicpu) : boolean;
var
op: tasmop;
begin
op:=ai.opcode;
is_macro_instruction :=
{ 'seq', 'sge', 'sgeu', 'sgt', 'sgtu', 'sle', 'sleu', 'sne', }
(op=A_SEQ) or (op = A_SGE) or (op=A_SGEU) or (op=A_SGT) or
(op=A_SGTU) or (op=A_SLE) or (op=A_SLEU) or (op=A_SNE)
{ JAL is not here! See comments in TCGMIPS.a_call_name. }
or (op=A_LA) or ((op=A_BC) and
not (ai.condition in [C_EQ,C_NE,C_GTZ,C_GEZ,C_LTZ,C_LEZ,C_COP1TRUE,C_COP1FALSE])) {or (op=A_JAL)}
or (op=A_REM) or (op=A_REMU)
{ DIV and DIVU are normally macros, but use $zero as first arg to generate a CPU instruction. }
or (((op=A_DIV) or (op=A_DIVU)) and
((ai.ops<>3) or (ai.oper[0]^.typ<>top_reg) or (ai.oper[0]^.reg<>NR_R0)))
or (op=A_MULO) or (op=A_MULOU)
{ A_LI is only a macro if the immediate is not in thez 16-bit range }
or (op=A_LI);
end;
procedure TMIPSInstrWriter.WriteInstruction(hp: Tai);
var
Op: TAsmOp;
@ -337,7 +316,7 @@ unit cpugas;
end;
else
begin
if is_macro_instruction(taicpu(hp)) and TMIPSGNUAssembler(owner).nomacro then
if taicpu(hp).is_macro and TMIPSGNUAssembler(owner).nomacro then
owner.writer.AsmWriteln(#9'.set'#9'macro');
s := #9 + gas_op2str[op] + cond2str[taicpu(hp).condition];
if taicpu(hp).ops > 0 then
@ -347,7 +326,7 @@ unit cpugas;
s := s + ',' + getopstr(taicpu(hp).oper[i]^);
end;
owner.writer.AsmWriteLn(s);
if is_macro_instruction(taicpu(hp)) and TMIPSGNUAssembler(owner).nomacro then
if taicpu(hp).is_macro and TMIPSGNUAssembler(owner).nomacro then
owner.writer.AsmWriteln(#9'.set'#9'nomacro');
end;
end;