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+ initial implementation of aarch64 register allocator
git-svn-id: trunk@29864 -
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@ -31,6 +31,7 @@ compiler/aarch64/ra64sri.inc svneol=native#text/plain
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compiler/aarch64/ra64sta.inc svneol=native#text/plain
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compiler/aarch64/ra64std.inc svneol=native#text/plain
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compiler/aarch64/ra64sup.inc svneol=native#text/plain
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compiler/aarch64/rgcpu.pas svneol=native#text/plain
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compiler/aarch64/symcpu.pas svneol=native#text/plain
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compiler/aasmbase.pas svneol=native#text/plain
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compiler/aasmdata.pas svneol=native#text/plain
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100
compiler/aarch64/rgcpu.pas
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compiler/aarch64/rgcpu.pas
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{
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit implements the SPARC specific class for the register
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allocator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************}
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unit rgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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aasmbase,aasmcpu,aasmtai,aasmdata,
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cgbase,cgutils,
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cpubase,
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globtype,
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rgobj;
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type
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trgcpu=class(trgobj)
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procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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protected
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procedure do_spill_op(list: tasmlist; op: tasmop; pos: tai; const spilltemp: treference; tempreg: tregister);
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end;
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implementation
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uses
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verbose,cutils,
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cgobj;
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procedure trgcpu.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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begin
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do_spill_op(list,A_LDR,pos,spilltemp,tempreg);
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end;
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procedure trgcpu.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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begin
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do_spill_op(list,A_STR,pos,spilltemp,tempreg);
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end;
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procedure trgcpu.do_spill_op(list: tasmlist; op: tasmop; pos: tai; const spilltemp: treference; tempreg: tregister);
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var
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helpins : tai;
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tmpref : treference;
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helplist : TAsmList;
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hreg : tregister;
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isload : boolean;
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begin
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isload:=op=A_LDR;
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{ offset out of range for regular load/store? }
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if simple_ref_type(op,reg_cgsize(tempreg),PF_None,spilltemp)<>sr_simple then
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begin
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helplist:=TAsmList.create;
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if getregtype(tempreg)=R_INTREGISTER then
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hreg:=tempreg
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else
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hreg:=cg.getaddressregister(helplist);
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cg.a_load_const_reg(helplist,OS_ADDR,spilltemp.offset,hreg);
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reference_reset_base(tmpref,spilltemp.base,0,sizeof(pint));
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tmpref.index:=hreg;
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if isload then
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helpins:=spilling_create_load(tmpref,tempreg)
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else
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helpins:=spilling_create_store(tempreg,tmpref);
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helplist.concat(helpins);
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add_cpu_interferences(helpins);
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list.insertlistafter(pos,helplist);
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helplist.free;
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end
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else if isload then
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inherited do_spill_read(list,pos,spilltemp,tempreg)
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else
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inherited do_spill_written(list,pos,spilltemp,tempreg)
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end;
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end.
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