*c <int64>:=-<longint> fixed (bug 4253)

git-svn-id: trunk@796 -

.gitattributes

@@ -6155,6 +6155,7 @@ tests/webtbs/tw4202.pp svneol=native#text/plain
 tests/webtbs/tw4215.pp svneol=native#text/plain
 tests/webtbs/tw4233.pp svneol=native#text/plain
 tests/webtbs/tw4247.pp svneol=native#text/plain
+tests/webtbs/tw4253.pp svneol=native#text/plain
 tests/webtbs/ub1873.pp svneol=native#text/plain
 tests/webtbs/ub1883.pp svneol=native#text/plain
 tests/webtbs/uw0555.pp svneol=native#text/plain

compiler/arm/cpubase.pas

@@ -293,6 +293,7 @@ unit cpubase;
       OS_ADDR = OS_32;
       { the natural int size for a processor,             }
       OS_INT = OS_32;
+      OS_SINT = OS_S32;
       { the maximum float size for a processor,           }
       OS_FLOAT = OS_F64;
       { the size of a vector register for a processor     }

compiler/i386/cpubase.inc

@@ -96,6 +96,7 @@
       OS_ADDR = OS_32;
       {# the natural int size for a processor,             }
       OS_INT = OS_32;
+      OS_SINT = OS_S32;
       {# the maximum float size for a processor,           }
       OS_FLOAT = OS_F80;
       {# the size of a vector register for a processor     }

compiler/m68k/cpubase.pas

@@ -223,6 +223,7 @@ unit cpubase;
       OS_ADDR = OS_32;
       {# the natural int size for a processor,             }
       OS_INT = OS_32;
+      OS_SINT = OS_S32;
       {# the maximum float size for a processor,           }
       OS_FLOAT = OS_F64;
       {# the size of a vector register for a processor     }

compiler/mips/cpubase.pas

@@ -290,6 +290,7 @@ unit cpubase;
       OS_ADDR = OS_32;
       { the natural int size for a processor,             }
       OS_INT = OS_32;
+      OS_SINT = OS_S32;
       { the maximum float size for a processor,           }
       OS_FLOAT = OS_F64;
       { the size of a vector register for a processor     }

compiler/ncgcnv.pas

@@ -101,6 +101,9 @@ interface
               end
             else
               location_force_reg(exprasmlist,location,newsize,false);
+{$ifndef cpu64bit}
+            // if is_signed(left.resulttype) and
+{$endif cpu64bit}
           end
         else
           begin

compiler/ncgmat.pas

@@ -219,8 +219,8 @@ implementation
         secondpass(left);
         { load left operator in a register }
         location_copy(location,left.location);
-        location_force_reg(exprasmlist,location,OS_INT,false);
+        location_force_reg(exprasmlist,location,OS_SINT,false);
-        cg.a_op_reg_reg(exprasmlist,OP_NEG,OS_INT,location.register,location.register);
+        cg.a_op_reg_reg(exprasmlist,OP_NEG,OS_SINT,location.register,location.register);
       end;
 
 

compiler/powerpc/cpubase.pas

@@ -262,6 +262,7 @@ uses
       OS_ADDR = OS_32;
       {# the natural int size for a processor,             }
       OS_INT = OS_32;
+      OS_SINT = OS_S32;
       {# the maximum float size for a processor,           }
       OS_FLOAT = OS_F64;
       {# the size of a vector register for a processor     }

compiler/sparc/cpubase.pas

@@ -237,6 +237,7 @@ uses
       OS_ADDR = OS_32;
       {# the natural int size for a processor,             }
       OS_INT = OS_32;
+      OS_SINT = OS_S32;
       {# the maximum float size for a processor,           }
       OS_FLOAT = OS_F64;
       {# the size of a vector register for a processor     }
@@ -330,7 +331,7 @@ uses
     procedure inverse_flags(var f: TResFlags);
     function inverse_cond(const c: TAsmCond): TAsmCond; {$ifdef USEINLINE}inline;{$endif USEINLINE}
     function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
-    
+
     function  flags_to_cond(const f: TResFlags) : TAsmCond;
     function cgsize2subreg(s:Tcgsize):Tsubregister;
     function reg_cgsize(const reg: tregister): tcgsize;

compiler/x86_64/cpubase.inc

@@ -78,6 +78,7 @@ const
       OS_ADDR = OS_64;
       { the natural int size for a processor,             }
       OS_INT = OS_64;
+      OS_SINT = OS_S64;
       { the maximum float size for a processor,           }
       OS_FLOAT = OS_F80;
       { the size of a vector register for a processor     }

tests/webtbs/tw4253.pp

@@ -0,0 +1,17 @@
+{ Source provided for Free Pascal Bug Report 4253 }
+{ Submitted by "Gerhard" on  2005-08-03 }
+{ e-mail: gs@g--s.de }
+program tirange ;
+
+  var
+//    Count : -high ( cardinal )..high ( cardinal ) ;
+    Count : int64 ;
+    long : longint ;
+
+  begin
+    count := -1 ;
+    writeln ( count ) ;  // gives -1
+    long := 1 ;
+    count := -long ;
+    writeln ( count ) ;  // gives 4294967295
+   end.