mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-09-08 13:39:28 +02:00
* some mips rtl compilation issues fixed
git-svn-id: trunk@20277 -
This commit is contained in:
florian
parent
58fbd386a3
commit
806ae36100
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -7669,6 +7669,8 @@ rtl/macos/sysutils.pp svneol=native#text/plain
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rtl/mips/int64p.inc svneol=native#text/plain
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rtl/mips/makefile.cpu svneol=native#text/plain
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rtl/mips/math.inc svneol=native#text/plain
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rtl/mips/mathu.inc svneol=native#text/plain
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rtl/mips/mathuh.inc svneol=native#text/plain
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rtl/mips/mips.inc svneol=native#text/plain
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rtl/mips/set.inc svneol=native#text/plain
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rtl/mips/setjump.inc svneol=native#text/plain
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@ -545,11 +545,18 @@ begin
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{$ifdef CPU64}
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Fppread:=do_syscall(syscall_nr_pread64,Fd,TSysParam(buf),nbytes,TSysParam(OffSet));
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{$else}
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{$ifdef CPUMIPS32}
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Fppread:=do_syscall(syscall_nr_pread64,Fd,TSysParam(buf),nbytes,0, { align parameters as required with dummy }
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{$ifdef FPC_BIG_ENDIAN} hi(offset),lo(offset){$endif}
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{$ifdef FPC_LITTLE_ENDIAN} lo(offset),hi(offset){$endif}
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);
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{$else CPUMIPS32}
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Fppread:=do_syscall(syscall_nr_pread,Fd,TSysParam(buf),nbytes,
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{$ifdef FPC_ABI_EABI} 0, { align parameters as required with dummy } {$endif FPC_ABI_EABI}
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{$ifdef FPC_BIG_ENDIAN} hi(offset),lo(offset){$endif}
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{$ifdef FPC_LITTLE_ENDIAN} lo(offset),hi(offset){$endif}
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);
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{$endif CPUMIPS32}
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{$endif}
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end;
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@ -559,11 +566,17 @@ begin
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{$ifdef CPU64}
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Fppwrite:=do_syscall(syscall_nr_pwrite64,Fd,TSysParam(buf),nbytes,TSysParam(OffSet));
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{$else}
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Fppwrite:=do_syscall(syscall_nr_pwrite,Fd,TSysParam(buf),nbytes,
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{$ifdef CPUMIPS32}
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Fppwrite:=do_syscall(syscall_nr_pwrite64,Fd,TSysParam(buf),nbytes,
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{$ifdef FPC_ABI_EABI} 0, { align parameters as required with dummy } {$endif FPC_ABI_EABI}
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{$ifdef FPC_BIG_ENDIAN} hi(offset),lo(offset){$endif}
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{$ifdef FPC_LITTLE_ENDIAN} lo(offset),hi(offset){$endif}
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);
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{$else CPUMIPS32}
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Fppwrite:=do_syscall(syscall_nr_pwrite,Fd,TSysParam(buf),nbytes,0, { align parameters as required with dummy }
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{$ifdef FPC_BIG_ENDIAN} hi(offset),lo(offset){$endif}
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{$ifdef FPC_LITTLE_ENDIAN} lo(offset),hi(offset){$endif}
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{$endif CPUMIPS32}
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{$endif}
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end;
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@ -1222,6 +1222,246 @@ Const
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{$endif cpuarm}
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{$ifdef cpumips}
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const
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TCGETA = $5401;
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TCSETA = $5402;
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TCSETAW = $5403;
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TCSETAF = $5404;
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TCSBRK = $5405;
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TCXONC = $5406;
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TCFLSH = $5407;
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TCGETS = $540d;
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TCSETS = $540e;
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TCSETSW = $540f;
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TCSETSF = $5410;
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TIOCEXCL = $740d;
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TIOCNXCL = $740e;
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TIOCOUTQ = $7472;
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TIOCSTI = $5472;
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TIOCMGET = $741d;
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TIOCMBIS = $741b;
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TIOCMBIC = $741c;
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TIOCMSET = $741a;
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TIOCPKT = $5470;
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TIOCPKT_DATA = $00;
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TIOCPKT_FLUSHREAD = $01;
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TIOCPKT_FLUSHWRITE = $02;
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TIOCPKT_STOP = $04;
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TIOCPKT_START = $08;
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TIOCPKT_NOSTOP = $10;
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TIOCPKT_DOSTOP = $20;
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TIOCPKT_IOCTL = $40;
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{$warning Check TIOCGWINSZ and TIOCSWINSZ on a real mips system }
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TIOCGWINSZ = $5414;
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TIOCSWINSZ = $5414;
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TIOCNOTTY = $5471;
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TIOCSETD = $7401;
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TIOCGETD = $7400;
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FIOCLEX = $6601;
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FIONCLEX = $6602;
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FIOASYNC = $667d;
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FIONBIO = $667e;
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FIOQSIZE = $667f;
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TIOCGLTC = $7474;
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TIOCSLTC = $7475;
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{$warning Check TIOCGPGRP and TIOCSPGRP on a real mips system }
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TIOCGPGRP = $540F;
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TIOCSPGRP = $5410;
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FIONREAD = $467f;
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TIOCINQ = FIONREAD;
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TIOCGETP = $7408;
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TIOCSETP = $7409;
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TIOCSETN = $740a;
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TIOCSBRK = $5427;
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TIOCCBRK = $5428;
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TIOCGSID = $7416;
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TIOCVHANGUP = $5437;
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TIOCSCTTY = $5480;
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TIOCGSOFTCAR = $5481;
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TIOCSSOFTCAR = $5482;
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TIOCLINUX = $5483;
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TIOCGSERIAL = $5484;
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TIOCSSERIAL = $5485;
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TCSBRKP = $5486;
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TIOCSERCONFIG = $5488;
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TIOCSERGWILD = $5489;
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TIOCSERSWILD = $548a;
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TIOCGLCKTRMIOS = $548b;
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TIOCSLCKTRMIOS = $548c;
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TIOCSERGSTRUCT = $548d;
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TIOCSERGETLSR = $548e;
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TIOCSERGETMULTI = $548f;
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TIOCSERSETMULTI = $5490;
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TIOCMIWAIT = $5491;
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TIOCGICOUNT = $5492;
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VINTR = 0;
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VQUIT = 1;
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VERASE = 2;
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VKILL = 3;
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VMIN = 4;
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VTIME = 5;
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VEOL2 = 6;
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VSWTC = 7;
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VSWTCH = VSWTC;
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VSTART = 8;
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VSTOP = 9;
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VSUSP = 10;
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const
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VREPRINT = 12;
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VDISCARD = 13;
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VWERASE = 14;
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VLNEXT = 15;
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VEOF = 16;
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VEOL = 17;
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IGNBRK = $0000001;
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BRKINT = $0000002;
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IGNPAR = $0000004;
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PARMRK = $0000010;
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INPCK = $0000020;
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ISTRIP = $0000040;
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INLCR = $0000100;
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IGNCR = $0000200;
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ICRNL = $0000400;
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IUCLC = $0001000;
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IXON = $0002000;
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IXANY = $0004000;
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IXOFF = $0010000;
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IMAXBEL = $0020000;
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IUTF8 = $0040000;
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OPOST = $0000001;
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OLCUC = $0000002;
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ONLCR = $0000004;
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OCRNL = $0000010;
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ONOCR = $0000020;
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ONLRET = $0000040;
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OFILL = $0000100;
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OFDEL = $0000200;
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NLDLY = $0000400;
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NL0 = $0000000;
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NL1 = $0000400;
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CRDLY = $0003000;
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CR0 = $0000000;
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CR1 = $0001000;
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CR2 = $0002000;
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CR3 = $0003000;
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TABDLY = $0014000;
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TAB0 = $0000000;
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TAB1 = $0004000;
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TAB2 = $0010000;
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TAB3 = $0014000;
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XTABS = $0014000;
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BSDLY = $0020000;
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BS0 = $0000000;
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BS1 = $0020000;
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VTDLY = $0040000;
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VT0 = $0000000;
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VT1 = $0040000;
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FFDLY = $0100000;
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FF0 = $0000000;
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FF1 = $0100000;
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CBAUD = $0010017;
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B0 = $0000000;
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B50 = $0000001;
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B75 = $0000002;
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B110 = $0000003;
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B134 = $0000004;
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B150 = $0000005;
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B200 = $0000006;
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B300 = $0000007;
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B600 = $0000010;
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B1200 = $0000011;
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B1800 = $0000012;
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B2400 = $0000013;
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B4800 = $0000014;
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B9600 = $0000015;
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B19200 = $0000016;
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B38400 = $0000017;
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EXTA = $B19200;
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EXTB = $B38400;
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CSIZE = $0000060;
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CS5 = $0000000;
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CS6 = $0000020;
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CS7 = $0000040;
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CS8 = $0000060;
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CSTOPB = $0000100;
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CREAD = $0000200;
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PARENB = $0000400;
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PARODD = $0001000;
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HUPCL = $0002000;
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CLOCAL = $0004000;
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CBAUDEX = $0010000;
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BOTHER = $0010000;
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B57600 = $0010001;
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B115200 = $0010002;
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B230400 = $0010003;
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B460800 = $0010004;
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B500000 = $0010005;
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B576000 = $0010006;
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B921600 = $0010007;
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B1000000 = $0010010;
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B1152000 = $0010011;
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B1500000 = $0010012;
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B2000000 = $0010013;
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B2500000 = $0010014;
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B3000000 = $0010015;
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B3500000 = $0010016;
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B4000000 = $0010017;
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CIBAUD = $002003600000;
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CMSPAR = $010000000000;
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CRTSCTS = $020000000000;
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IBSHIFT = 16;
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ISIG = $0000001;
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ICANON = $0000002;
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XCASE = $0000004;
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ECHO = $0000010;
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ECHOE = $0000020;
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ECHOK = $0000040;
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ECHONL = $0000100;
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NOFLSH = $0000200;
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IEXTEN = $0000400;
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ECHOCTL = $0001000;
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ECHOPRT = $0002000;
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ECHOKE = $0004000;
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FLUSHO = $0020000;
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PENDIN = $0040000;
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TOSTOP = $0100000;
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ITOSTOP = TOSTOP;
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EXTPROC = $0200000;
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TIOCSER_TEMT = $01;
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TCOOFF = 0;
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TCOON = 1;
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TCIOFF = 2;
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TCION = 3;
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TCIFLUSH = 0;
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TCOFLUSH = 1;
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TCIOFLUSH = 2;
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TCSANOW = TCSETS;
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TCSADRAIN = TCSETSW;
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TCSAFLUSH = TCSETSF;
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{$endif CPUMIPS}
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Type
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winsize = record
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ws_row,
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146
rtl/mips/mathu.inc
Normal file
146
rtl/mips/mathu.inc
Normal file
@ -0,0 +1,146 @@
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{
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This file is part of the Free Pascal run time library.
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Copyright (c) 1999-2000 by Florian Klaempfl
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member of the Free Pascal development team
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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{ exported by the system unit }
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//!!!function get_fsr : dword;external name 'FPC_GETFSR';
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//!!!procedure set_fsr(fsr : dword);external name 'FPC_SETFSR';
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function FPUExceptionMaskToSoftFloatMask(const Mask: TFPUExceptionMask): byte;
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begin
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result:=0;
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if exInvalidOp in Mask then
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result:=result or (1 shl ord(exInvalidOp));
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if exDenormalized in Mask then
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result:=result or (1 shl ord(exDenormalized));
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if exZeroDivide in Mask then
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result:=result or (1 shl ord(exZeroDivide));
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if exOverflow in Mask then
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result:=result or (1 shl ord(exOverflow));
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if exUnderflow in Mask then
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result:=result or (1 shl ord(exUnderflow));
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if exPrecision in Mask then
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result:=result or (1 shl ord(exPrecision));
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end;
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function GetRoundMode: TFPURoundingMode;
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begin
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//!!! result:=TFPURoundingMode(get_fsr shr 30);
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end;
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function SetRoundMode(const RoundMode: TFPURoundingMode): TFPURoundingMode;
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begin
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case (RoundMode) of
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rmNearest :
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softfloat_rounding_mode := float_round_nearest_even;
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rmTruncate :
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softfloat_rounding_mode := float_round_to_zero;
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rmUp :
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softfloat_rounding_mode := float_round_up;
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rmDown :
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softfloat_rounding_mode := float_round_down;
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end;
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//!!! set_fsr((get_fsr and $3fffffff) or (dword(RoundMode) shl 30));
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//!!! result:=TFPURoundingMode(get_fsr shr 30);
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end;
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function GetPrecisionMode: TFPUPrecisionMode;
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begin
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result:=pmDouble;
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end;
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function SetPrecisionMode(const Precision: TFPUPrecisionMode): TFPUPrecisionMode;
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begin
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result:=pmDouble;
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end;
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function GetExceptionMask: TFPUExceptionMask;
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var
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fsr : dword;
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begin
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//!!! fsr:=get_fsr;
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result:=[];
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{ invalid operation: bit 27 }
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if (fsr and (1 shl 27))=0 then
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include(result,exInvalidOp);
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{ zero divide: bit 24 }
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if (fsr and (1 shl 24))=0 then
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include(result,exInvalidOp);
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{ overflow: bit 26 }
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if (fsr and (1 shl 26))=0 then
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include(result,exInvalidOp);
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{ underflow: bit 25 }
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if (fsr and (1 shl 25))=0 then
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include(result,exUnderflow);
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{ Precision (inexact result): bit 23 }
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if (fsr and (1 shl 23))=0 then
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include(result,exPrecision);
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end;
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function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
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var
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fsr : dword;
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begin
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//!!! fsr:=get_fsr;
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{ invalid operation: bit 27 }
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if (exInvalidOp in mask) then
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fsr:=fsr and not(1 shl 27)
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else
|
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fsr:=fsr or (1 shl 27);
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|
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{ zero divide: bit 24 }
|
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if (exZeroDivide in mask) then
|
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fsr:=fsr and not(1 shl 24)
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else
|
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fsr:=fsr or (1 shl 24);
|
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|
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{ overflow: bit 26 }
|
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if (exOverflow in mask) then
|
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fsr:=fsr and not(1 shl 26)
|
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else
|
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fsr:=fsr or (1 shl 26);
|
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|
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{ underflow: bit 25 }
|
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if (exUnderflow in mask) then
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fsr:=fsr and not(1 shl 25)
|
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else
|
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fsr:=fsr or (1 shl 25);
|
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|
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{ Precision (inexact result): bit 23 }
|
||||
if (exPrecision in mask) then
|
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fsr:=fsr and not(1 shl 23)
|
||||
else
|
||||
fsr:=fsr or (1 shl 23);
|
||||
|
||||
{ update control register contents }
|
||||
//!!! set_fsr(fsr);
|
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|
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softfloat_exception_mask:=FPUExceptionMaskToSoftFloatMask(mask);
|
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end;
|
||||
|
||||
|
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procedure ClearExceptions(RaisePending: Boolean =true);
|
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begin
|
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//!!! set_fsr(get_fsr and $fffffc1f);
|
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end;
|
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|
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29
rtl/mips/mathuh.inc
Normal file
29
rtl/mips/mathuh.inc
Normal file
@ -0,0 +1,29 @@
|
||||
{
|
||||
This file is part of the Free Pascal run time library.
|
||||
Copyright (c) 1999-2000 by Florian Klaempfl
|
||||
member of the Free Pascal development team
|
||||
|
||||
See the file COPYING.FPC, included in this distribution,
|
||||
for details about the copyright.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
|
||||
**********************************************************************}
|
||||
|
||||
type
|
||||
TFPURoundingMode = (rmNearest, rmDown, rmUp, rmTruncate);
|
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TFPUPrecisionMode = (pmSingle, pmReserved, pmDouble, pmExtended);
|
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TFPUException = (exInvalidOp, exDenormalized, exZeroDivide,
|
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exOverflow, exUnderflow, exPrecision);
|
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TFPUExceptionMask = set of TFPUException;
|
||||
|
||||
function GetRoundMode: TFPURoundingMode;
|
||||
function SetRoundMode(const RoundMode: TFPURoundingMode): TFPURoundingMode;
|
||||
function GetPrecisionMode: TFPUPrecisionMode;
|
||||
function SetPrecisionMode(const Precision: TFPUPrecisionMode): TFPUPrecisionMode;
|
||||
function GetExceptionMask: TFPUExceptionMask;
|
||||
function SetExceptionMask(const Mask: TFPUExceptionMask): TFPUExceptionMask;
|
||||
procedure ClearExceptions(RaisePending: Boolean =true);
|
||||
|
||||
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