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Fixed assembler calling command line for cpus>ARMv5TE. EDSP instructions will generate errors while assembling, due to RTL assembler routines

Browse Source 
Updated boot code for all Cortex-M3 controllers, and sc32442b to use weak linking for exception tables.
Cortex-M3 devices now also share initialization routine to simplify maintenance
STM32F10x classes now have specific units which fit the interrupt source names and counts

git-svn-id: branches/laksen/arm-embedded@22581 -
This commit is contained in:
Jeppe Johansen 2012-10-08 03:15:40 +00:00
parent 8e00978108
commit 80bb3febea
16 changed files with 5011 additions and 1604 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
.gitattributes vendored
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@ -7425,12 +7425,17 @@ rtl/darwin/x86_64/sighnd.inc svneol=native#text/plain
rtl/embedded/Makefile svneol=native#text/plain
rtl/embedded/Makefile.fpc svneol=native#text/plain
rtl/embedded/arm/at91sam7x256.pp svneol=native#text/plain
rtl/embedded/arm/cortexm3_start.inc svneol=native#text/pascal
rtl/embedded/arm/lm3fury.pp svneol=native#text/pascal
rtl/embedded/arm/lm3tempest.pp svneol=native#text/pascal
rtl/embedded/arm/lpc1768.pp svneol=native#text/pascal
rtl/embedded/arm/lpc21x4.pp svneol=native#text/plain
rtl/embedded/arm/sc32442b.pp svneol=native#text/pascal
rtl/embedded/arm/stm32f103.pp svneol=native#text/plain
rtl/embedded/arm/stm32f10x_conn.pp svneol=native#text/pascal
rtl/embedded/arm/stm32f10x_hd.pp svneol=native#text/pascal
rtl/embedded/arm/stm32f10x_ld.pp svneol=native#text/pascal
rtl/embedded/arm/stm32f10x_md.pp svneol=native#text/pascal
rtl/embedded/arm/stm32f10x_xl.pp svneol=native#text/pascal
rtl/embedded/avr/atmega128.pp svneol=native#text/plain
rtl/embedded/avr/start.inc svneol=native#text/plain
rtl/embedded/buildrtl.lpi svneol=native#text/plain

3
compiler/arm/agarmgas.pas
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@ -109,7 +109,8 @@ unit agarmgas;
if current_settings.cputype=cpu_armv7m then
result:='-march=armv7m -mthumb -mthumb-interwork '+result
else
// EDSP instructions in RTL require armv5te at least to not generate error
else if current_settings.cputype >= cpu_armv5te then
result:='-march='+cputype_to_gas_march[current_settings.cputype]+' '+result;
if target_info.abi = abi_eabihf then

8
compiler/arm/cpuinfo.pas
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@ -365,7 +365,7 @@ Const
// ct_stm32f103rb,
(
controllertypestr:'STM32F103RB';
controllerunitstr:'STM32F103';
controllerunitstr:'STM32F10X_MD';
flashbase:$08000000;
flashsize:$00020000;
srambase:$20000000;
@ -374,16 +374,16 @@ Const
// ct_stm32f103re,
(
controllertypestr:'STM32F103RE';
controllerunitstr:'STM32F103';
controllerunitstr:'STM32F10X_HD';
flashbase:$08000000;
flashsize:$00080000;
srambase:$20000000;
sramsize:$00010000
),
// ct_stm32f103re,
// ct_stm32f103c4t,
(
controllertypestr:'STM32F103C4T';
controllerunitstr:'STM32F103';
controllerunitstr:'STM32F10X_LD';
flashbase:$08000000;
flashsize:$00004000;
srambase:$20000000;

107
rtl/embedded/Makefile
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@ -1,5 +1,5 @@
#
# Don't edit, this file is generated by FPCMake Version 2.0.0 [2012/04/25]
# Don't edit, this file is generated by FPCMake Version 2.0.0 [2012/09/26]
#
default: all
MAKEFILETARGETS=i386-linux i386-go32v2 i386-win32 i386-os2 i386-freebsd i386-beos i386-haiku i386-netbsd i386-solaris i386-qnx i386-netware i386-openbsd i386-wdosx i386-darwin i386-emx i386-watcom i386-netwlibc i386-wince i386-embedded i386-symbian i386-nativent i386-iphonesim m68k-linux m68k-freebsd m68k-netbsd m68k-amiga m68k-atari m68k-openbsd m68k-palmos m68k-embedded powerpc-linux powerpc-netbsd powerpc-amiga powerpc-macos powerpc-darwin powerpc-morphos powerpc-embedded powerpc-wii powerpc-aix sparc-linux sparc-netbsd sparc-solaris sparc-embedded x86_64-linux x86_64-freebsd x86_64-netbsd x86_64-solaris x86_64-openbsd x86_64-darwin x86_64-win64 x86_64-embedded arm-linux arm-palmos arm-darwin arm-wince arm-gba arm-nds arm-embedded arm-symbian powerpc64-linux powerpc64-darwin powerpc64-embedded powerpc64-aix avr-embedded armeb-linux armeb-embedded mips-linux mipsel-linux jvm-java jvm-android
@ -210,6 +210,14 @@ endif
ifeq ($(OS_TARGET),linux)
linuxHier=1
endif
ifndef CROSSCOMPILE
BUILDFULLNATIVE=1
export BUILDFULLNATIVE
endif
ifdef BUILDFULLNATIVE
BUILDNATIVE=1
export BUILDNATIVE
endif
export OS_TARGET OS_SOURCE ARCH CPU_TARGET CPU_SOURCE FULL_TARGET FULL_SOURCE TARGETSUFFIX SOURCESUFFIX CROSSCOMPILE
ifdef FPCDIR
override FPCDIR:=$(subst \,/,$(FPCDIR))
@ -311,7 +319,7 @@ CPU_UNITS=
SYSINIT_UNITS=
ifeq ($(ARCH),arm)
ifeq ($(SUBARCH),armv7m)
CPU_UNITS=lm3fury lm3tempest stm32f103 lpc1768 # thumb2_bare
CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1768 # thumb2_bare
endif
ifeq ($(SUBARCH),armv4t)
CPU_UNITS=lpc21x4 at91sam7x256 sc32442b
@ -1681,17 +1689,12 @@ endif
endif
ifdef CREATESHARED
override FPCOPT+=-Cg
ifeq ($(CPU_TARGET),i386)
override FPCOPT+=-Aas
endif
endif
ifeq ($(findstring 2.0.,$(FPC_VERSION)),)
ifneq ($(findstring $(OS_TARGET),freebsd openbsd netbsd linux solaris),)
ifeq ($(CPU_TARGET),x86_64)
override FPCOPT+=-Cg
endif
endif
endif
ifdef LINKSHARED
endif
ifdef OPT
@ -2066,6 +2069,96 @@ endif
fpc_makefile_sub2: $(addsuffix _makefile_dirs,$(TARGET_DIRS) $(TARGET_EXAMPLEDIRS))
fpc_makefile_dirs: fpc_makefile_sub1 fpc_makefile_sub2
fpc_makefiles: fpc_makefile fpc_makefile_dirs
ifdef TARGET_DIRS_TARGET_DIRS
TARGET_DIRS_all:
$(MAKE) -C TARGET_DIRS all
TARGET_DIRS_debug:
$(MAKE) -C TARGET_DIRS debug
TARGET_DIRS_smart:
$(MAKE) -C TARGET_DIRS smart
TARGET_DIRS_release:
$(MAKE) -C TARGET_DIRS release
TARGET_DIRS_units:
$(MAKE) -C TARGET_DIRS units
TARGET_DIRS_examples:
$(MAKE) -C TARGET_DIRS examples
TARGET_DIRS_shared:
$(MAKE) -C TARGET_DIRS shared
TARGET_DIRS_install:
$(MAKE) -C TARGET_DIRS install
TARGET_DIRS_sourceinstall:
$(MAKE) -C TARGET_DIRS sourceinstall
TARGET_DIRS_exampleinstall:
$(MAKE) -C TARGET_DIRS exampleinstall
TARGET_DIRS_distinstall:
$(MAKE) -C TARGET_DIRS distinstall
TARGET_DIRS_zipinstall:
$(MAKE) -C TARGET_DIRS zipinstall
TARGET_DIRS_zipsourceinstall:
$(MAKE) -C TARGET_DIRS zipsourceinstall
TARGET_DIRS_zipexampleinstall:
$(MAKE) -C TARGET_DIRS zipexampleinstall
TARGET_DIRS_zipdistinstall:
$(MAKE) -C TARGET_DIRS zipdistinstall
TARGET_DIRS_clean:
$(MAKE) -C TARGET_DIRS clean
TARGET_DIRS_distclean:
$(MAKE) -C TARGET_DIRS distclean
TARGET_DIRS_cleanall:
$(MAKE) -C TARGET_DIRS cleanall
TARGET_DIRS_info:
$(MAKE) -C TARGET_DIRS info
TARGET_DIRS_makefiles:
$(MAKE) -C TARGET_DIRS makefiles
TARGET_DIRS:
$(MAKE) -C TARGET_DIRS all
.PHONY: TARGET_DIRS_all TARGET_DIRS_debug TARGET_DIRS_smart TARGET_DIRS_release TARGET_DIRS_units TARGET_DIRS_examples TARGET_DIRS_shared TARGET_DIRS_install TARGET_DIRS_sourceinstall TARGET_DIRS_exampleinstall TARGET_DIRS_distinstall TARGET_DIRS_zipinstall TARGET_DIRS_zipsourceinstall TARGET_DIRS_zipexampleinstall TARGET_DIRS_zipdistinstall TARGET_DIRS_clean TARGET_DIRS_distclean TARGET_DIRS_cleanall TARGET_DIRS_info TARGET_DIRS_makefiles TARGET_DIRS
endif
ifdef TARGET_EXAMPLEDIRS_TARGET_EXAMPLEDIRS
TARGET_EXAMPLEDIRS_all:
$(MAKE) -C TARGET_EXAMPLEDIRS all
TARGET_EXAMPLEDIRS_debug:
$(MAKE) -C TARGET_EXAMPLEDIRS debug
TARGET_EXAMPLEDIRS_smart:
$(MAKE) -C TARGET_EXAMPLEDIRS smart
TARGET_EXAMPLEDIRS_release:
$(MAKE) -C TARGET_EXAMPLEDIRS release
TARGET_EXAMPLEDIRS_units:
$(MAKE) -C TARGET_EXAMPLEDIRS units
TARGET_EXAMPLEDIRS_examples:
$(MAKE) -C TARGET_EXAMPLEDIRS examples
TARGET_EXAMPLEDIRS_shared:
$(MAKE) -C TARGET_EXAMPLEDIRS shared
TARGET_EXAMPLEDIRS_install:
$(MAKE) -C TARGET_EXAMPLEDIRS install
TARGET_EXAMPLEDIRS_sourceinstall:
$(MAKE) -C TARGET_EXAMPLEDIRS sourceinstall
TARGET_EXAMPLEDIRS_exampleinstall:
$(MAKE) -C TARGET_EXAMPLEDIRS exampleinstall
TARGET_EXAMPLEDIRS_distinstall:
$(MAKE) -C TARGET_EXAMPLEDIRS distinstall
TARGET_EXAMPLEDIRS_zipinstall:
$(MAKE) -C TARGET_EXAMPLEDIRS zipinstall
TARGET_EXAMPLEDIRS_zipsourceinstall:
$(MAKE) -C TARGET_EXAMPLEDIRS zipsourceinstall
TARGET_EXAMPLEDIRS_zipexampleinstall:
$(MAKE) -C TARGET_EXAMPLEDIRS zipexampleinstall
TARGET_EXAMPLEDIRS_zipdistinstall:
$(MAKE) -C TARGET_EXAMPLEDIRS zipdistinstall
TARGET_EXAMPLEDIRS_clean:
$(MAKE) -C TARGET_EXAMPLEDIRS clean
TARGET_EXAMPLEDIRS_distclean:
$(MAKE) -C TARGET_EXAMPLEDIRS distclean
TARGET_EXAMPLEDIRS_cleanall:
$(MAKE) -C TARGET_EXAMPLEDIRS cleanall
TARGET_EXAMPLEDIRS_info:
$(MAKE) -C TARGET_EXAMPLEDIRS info
TARGET_EXAMPLEDIRS_makefiles:
$(MAKE) -C TARGET_EXAMPLEDIRS makefiles
TARGET_EXAMPLEDIRS:
$(MAKE) -C TARGET_EXAMPLEDIRS all
.PHONY: TARGET_EXAMPLEDIRS_all TARGET_EXAMPLEDIRS_debug TARGET_EXAMPLEDIRS_smart TARGET_EXAMPLEDIRS_release TARGET_EXAMPLEDIRS_units TARGET_EXAMPLEDIRS_examples TARGET_EXAMPLEDIRS_shared TARGET_EXAMPLEDIRS_install TARGET_EXAMPLEDIRS_sourceinstall TARGET_EXAMPLEDIRS_exampleinstall TARGET_EXAMPLEDIRS_distinstall TARGET_EXAMPLEDIRS_zipinstall TARGET_EXAMPLEDIRS_zipsourceinstall TARGET_EXAMPLEDIRS_zipexampleinstall TARGET_EXAMPLEDIRS_zipdistinstall TARGET_EXAMPLEDIRS_clean TARGET_EXAMPLEDIRS_distclean TARGET_EXAMPLEDIRS_cleanall TARGET_EXAMPLEDIRS_info TARGET_EXAMPLEDIRS_makefiles TARGET_EXAMPLEDIRS
endif
all: fpc_all
debug: fpc_debug
smart: fpc_smart

2
rtl/embedded/Makefile.fpc
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@ -49,7 +49,7 @@ SYSINIT_UNITS=
ifeq ($(ARCH),arm)
ifeq ($(SUBARCH),armv7m)
CPU_UNITS=lm3fury lm3tempest stm32f103 lpc1768 # thumb2_bare
CPU_UNITS=lm3fury lm3tempest stm32f10x_ld stm32f10x_md stm32f10x_hd stm32f10x_xl stm32f10x_conn lpc1768 # thumb2_bare
endif
ifeq ($(SUBARCH),armv4t)
CPU_UNITS=lpc21x4 at91sam7x256 sc32442b

52
rtl/embedded/arm/cortexm3_start.inc Normal file
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@ -0,0 +1,52 @@
var
_stack_top: record end; external name '_stack_top';
_data: record end; external name '_data';
_edata: record end; external name '_edata';
_etext: record end; external name '_etext';
_bss_start: record end; external name '_bss_start';
_bss_end: record end; external name '_bss_end';
procedure Pascalmain; external name 'PASCALMAIN';
procedure HaltProc; assembler; nostackframe; public name'_haltproc';
asm
.Lloop:
b .Lloop
end;
procedure Startup; assembler; nostackframe; [public, alias: '_START'];
asm
ldr r1,.L_etext
ldr r2,.L_data
ldr r3,.L_edata
.Lcopyloop:
cmp r2,r3
ittt ls
ldrls r0,[r1],#4
strls r0,[r2],#4
bls .Lcopyloop
// clear onboard ram
ldr r1,.L_bss_start
ldr r2,.L_bss_end
mov r0,#0
.Lzeroloop:
cmp r1,r2
itt ls
strls r0,[r1],#4
bls .Lzeroloop
bl PASCALMAIN
b HaltProc
.L_bss_start:
.long _bss_start
.L_bss_end:
.long _bss_end
.L_etext:
.long _etext
.L_data:
.long _data
.L_edata:
.long _edata
end;

423
rtl/embedded/arm/lm3fury.pp
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@ -61,234 +61,211 @@ unit lm3fury;
rcgc1 :dword absolute (sysconoffset+$104);
rcgc2 :dword absolute (sysconoffset+$108);
var
NMI_Handler,
HardFault_Handler,
MemManage_Handler,
BusFault_Handler,
UsageFault_Handler,
SWI_Handler,
DebugMonitor_Handler,
PendingSV_Handler,
Systick_Handler,UART0intvector: pointer;
implementation
var
_data: record end; external name '_data';
_edata: record end; external name '_edata';
_etext: record end; external name '_etext';
_bss_start: record end; external name '_bss_start';
_bss_end: record end; external name '_bss_end';
_stack_top: record end; external name '_stack_top';
procedure NMI_interrupt; external name 'NMI_interrupt';
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
procedure MemManage_interrupt; external name 'MemManage_interrupt';
procedure BusFault_interrupt; external name 'BusFault_interrupt';
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
procedure SWI_interrupt; external name 'SWI_interrupt';
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
procedure SysTick_interrupt; external name 'SysTick_interrupt';
procedure GPIO_Port_A_Interrupt; external name 'GPIO_Port_A_Interrupt';
procedure GPIO_Port_B_Interrupt; external name 'GPIO_Port_B_Interrupt';
procedure GPIO_Port_C_Interrupt; external name 'GPIO_Port_C_Interrupt';
procedure GPIO_Port_D_Interrupt; external name 'GPIO_Port_D_Interrupt';
procedure GPIO_Port_E_Interrupt; external name 'GPIO_Port_E_Interrupt';
procedure UART0_Interrupt; external name 'UART0_Interrupt';
procedure UART1_Interrupt; external name 'UART1_Interrupt';
procedure SSI0_Interrupt; external name 'SSI0_Interrupt';
procedure I2C0_Interrupt; external name 'I2C0_Interrupt';
procedure ADC0_Sequence_0_Interrupt; external name 'ADC0_Sequence_0_Interrupt';
procedure ADC0_Sequence_1_Interrupt; external name 'ADC0_Sequence_1_Interrupt';
procedure ADC0_Sequence_2_Interrupt; external name 'ADC0_Sequence_2_Interrupt';
procedure ADC0_Sequence_3_Interrupt; external name 'ADC0_Sequence_3_Interrupt';
procedure Watchdog_Timer_0_Interrupt; external name 'Watchdog_Timer_0_Interrupt';
procedure Timer_0A_Interrupt; external name 'Timer_0A_Interrupt';
procedure Timer_0B_Interrupt; external name 'Timer_0B_Interrupt';
procedure Timer_1A_Interrupt; external name 'Timer_1A_Interrupt';
procedure Timer_1B_Interrupt; external name 'Timer_1B_Interrupt';
procedure Timer_2A_Interrupt; external name 'Timer_2A_Interrupt';
procedure Timer_2B_Interrupt; external name 'Timer_2B_Interrupt';
procedure Analog_Comparator_0_Interrupt; external name 'Analog_Comparator_0_Interrupt';
procedure Analog_Comparator_1_Interrupt; external name 'Analog_Comparator_1_Interrupt';
procedure Analog_Comparator_2_Interrupt; external name 'Analog_Comparator_2_Interrupt';
procedure System_Control_Interrupt; external name 'System_Control_Interrupt';
procedure Flash_Memory_Control_Interrupt; external name 'Flash_Memory_Control_Interrupt';
procedure GPIO_Port_F_Interrupt; external name 'GPIO_Port_F_Interrupt';
procedure GPIO_Port_G_Interrupt; external name 'GPIO_Port_G_Interrupt';
procedure GPIO_Port_H_Interrupt; external name 'GPIO_Port_H_Interrupt';
procedure UART2_Interrupt; external name 'UART2_Interrupt';
procedure SSI1_Interrupt; external name 'SSI1_Interrupt';
procedure Timer_3A_Interrupt; external name 'Timer_3A_Interrupt';
procedure Timer_3B_Interrupt; external name 'Timer_3B_Interrupt';
procedure I2C1_Interrupt; external name 'I2C1_Interrupt';
procedure Hibernation_Module_Interrupt; external name 'Hibernation_Module_Interrupt';
procedure PASCALMAIN; external name 'PASCALMAIN';
{$i cortexm3_start.inc}
procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
asm
.Lhalt:
b .Lhalt
end;
procedure _FPC_start; assembler; nostackframe;
label
_start;
asm
.init
.align 16
.long _stack_top // First entry in NVIC table is the new stack pointer
.long _start+1 //gjb changed from stm32f version to avoid invstate error when interrupt fires
//b _start // Reset
.long _start+1
//b .LNMI_Addr // Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
.long _start+1
//b .LHardFault_Addr // All class of fault
.long _start+1
//b .LMemManage_Addr // Memory management
.long _start+1
//b .LBusFault_Addr // Pre-fetch fault, memory access fault
.long _start+1
//b .LUsageFault_Addr // Undefined instruction or illegal state
.long _start+1
//nop // Reserved
.long _start+1
//nop // Reserved
.long _start+1
//nop // Reserved
.long _start+1
//nop // Reserved
.long _start+1
//b .LSWI_Addr // Software Interrupt vector now SVC
.long _start+1
//b .LDebugMonitor_Addr // Debug Monitor
.long _start+1
//nop // Reserved
.long _start+1
//b .LPendingSV_Addr // Pendable request for system service
.long _start+1
//b .LSystick_Addr // System tick timer
//16
.long .LDefaultHandler+1 //GPIOA #0
.long .LDefaultHandler+1 //GPIOB
.long .LDefaultHandler+1 //GPIOC
.long .LDefaultHandler+1 //GPIOD
.long .LDefaultHandler+1 //GPIOE
.long .LUART0handler+1 //.LDefaultHandler+1 //UART0
.long .LDefaultHandler+1 //UART1
.long .LDefaultHandler+1 //SSI0
//24
.long .LDefaultHandler+1 //I2C0 #8
.long .LDefaultHandler+1 //PWMF
.long .LDefaultHandler+1 //PWMG0
.long .LDefaultHandler+1 //PWMG1
.long .LDefaultHandler+1 //PWMG2
.long .LDefaultHandler+1 //QEI0
.long .LDefaultHandler+1 //ADC0S0
.long .LDefaultHandler+1 //ADC0S1
//32
.long .LDefaultHandler+1 //ADC0S2 #16
.long .LDefaultHandler+1 //ADC0S3
.long .LDefaultHandler+1 //WDGTimer01
.long .LDefaultHandler+1 //T0A
.long .LDefaultHandler+1 //T0B
.long .LDefaultHandler+1 //T1A
.long .LDefaultHandler+1 //T1B
.long .LDefaultHandler+1 //T2A
//40
.long .LDefaultHandler+1 //T2B #24
.long .LDefaultHandler+1 //COMP0
.long .LDefaultHandler+1 //COMP1
.long .LDefaultHandler+1 //COMP2
.long .LDefaultHandler+1 //SYSCON
.long .LDefaultHandler+1 //FLASH
.long .LDefaultHandler+1 //GPIOF
.long .LDefaultHandler+1 //GPIOG
//48
.long .LDefaultHandler+1 //GPIOH #32
.long .LDefaultHandler+1 //UART2
.long .LDefaultHandler+1 //SSI1
.long .LDefaultHandler+1 //T3A
.long .LDefaultHandler+1 //T3B
.long .LDefaultHandler+1 //I2C1
.long .LDefaultHandler+1 //QEI1
.long .LDefaultHandler+1 //CAN0
//56
.long .LDefaultHandler+1 //CAN1 #40
.long .LDefaultHandler+1 //res
.long .LDefaultHandler+1 //ETH
.long .LDefaultHandler+1 //res
.long .LDefaultHandler+1 //USB
.long .LDefaultHandler+1 //PWMG3
.long .LDefaultHandler+1 //UDMAS
.long .LDefaultHandler+1 //UDMAE
//64
.long .LDefaultHandler+1 //ADC1S0 #48
.long .LDefaultHandler+1 //ADC1S1
.long .LDefaultHandler+1 //ADC1S2
.long .LDefaultHandler+1 //ADC1S3
.long .LDefaultHandler+1 //I2S0
.long .LDefaultHandler+1 //EPI
.long .LDefaultHandler+1 //GPIOJ
.long .LDefaultHandler+1 //res #55
.LNMI_Addr:
ldr r0,.L1
ldr pc,[r0]
.LHardFault_Addr:
ldr r0,.L2
ldr pc,[r0]
.LMemManage_Addr:
ldr r0,.L3
ldr pc,[r0]
.LBusFault_Addr:
ldr r0,.L4
ldr pc,[r0]
.LUsageFault_Addr:
ldr r0,.L5
ldr pc,[r0]
.LSWI_Addr:
ldr r0,.L6
ldr pc,[r0]
.LDebugMonitor_Addr:
ldr r0,.L7
ldr pc,[r0]
.LPendingSV_Addr:
ldr r0,.L8
ldr pc,[r0]
.LSystick_Addr:
ldr r0,.L9
ldr pc,[r0]
.LUART0handler:
ldr r0,.L10
ldr pc,[r0]
.L1:
.long NMI_Handler
.L2:
.long HardFault_Handler
.L3:
.long MemManage_Handler
.L4:
.long BusFault_Handler
.L5:
.long UsageFault_Handler
.L6:
.long SWI_Handler
.L7:
.long DebugMonitor_Handler
.L8:
.long PendingSV_Handler
.L9:
.long Systick_Handler
.L10:
.long UART0IntVector
procedure Vectors; assembler; nostackframe;
label interrupt_vectors;
asm
.section ".init.interrupt_vectors"
interrupt_vectors:
.long _stack_top
.long Startup
.long NMI_interrupt
.long Hardfault_interrupt
.long MemManage_interrupt
.long BusFault_interrupt
.long UsageFault_interrupt
.long 0
.long 0
.long 0
.long 0
.long SWI_interrupt
.long DebugMonitor_interrupt
.long 0
.long PendingSV_interrupt
.long SysTick_interrupt
.globl _start
.text
_start:
// Copy initialized data to ram
ldr r1,.L_etext
ldr r2,.L_data
ldr r3,.L_edata
.Lcopyloop:
cmp r2,r3
ittt ls
ldrls r0,[r1],#4
strls r0,[r2],#4
bls .Lcopyloop
// clear onboard ram
ldr r1,.L_bss_start
ldr r2,.L_bss_end
mov r0,#0
.Lzeroloop:
cmp r1,r2
itt ls
strls r0,[r1],#4
bls .Lzeroloop
b PASCALMAIN
b _FPC_haltproc
.L_bss_start:
.long _bss_start
.L_bss_end:
.long _bss_end
.L_etext:
.long _etext
.L_data:
.long _data
.L_edata:
.long _edata
.LDefaultHandlerAddr:
.long .LDefaultHandler
// default irq handler just returns
.LDefaultHandler:
mov pc,r14
end;
.long GPIO_Port_A_Interrupt
.long GPIO_Port_B_Interrupt
.long GPIO_Port_C_Interrupt
.long GPIO_Port_D_Interrupt
.long GPIO_Port_E_Interrupt
.long UART0_Interrupt
.long UART1_Interrupt
.long SSI0_Interrupt
.long I2C0_Interrupt
.long 0
.long 0
.long 0
.long 0
.long 0
.long ADC0_Sequence_0_Interrupt
.long ADC0_Sequence_1_Interrupt
.long ADC0_Sequence_2_Interrupt
.long ADC0_Sequence_3_Interrupt
.long Watchdog_Timer_0_Interrupt
.long Timer_0A_Interrupt
.long Timer_0B_Interrupt
.long Timer_1A_Interrupt
.long Timer_1B_Interrupt
.long Timer_2A_Interrupt
.long Timer_2B_Interrupt
.long Analog_Comparator_0_Interrupt
.long Analog_Comparator_1_Interrupt
.long Analog_Comparator_2_Interrupt
.long System_Control_Interrupt
.long Flash_Memory_Control_Interrupt
.long GPIO_Port_F_Interrupt
.long GPIO_Port_G_Interrupt
.long GPIO_Port_H_Interrupt
.long UART2_Interrupt
.long SSI1_Interrupt
.long Timer_3A_Interrupt
.long Timer_3B_Interrupt
.long I2C1_Interrupt
.long 0
.long 0
.long 0
.long 0
.long 0
.long Hibernation_Module_Interrupt
.weak NMI_interrupt
.weak Hardfault_interrupt
.weak MemManage_interrupt
.weak BusFault_interrupt
.weak UsageFault_interrupt
.weak SWI_interrupt
.weak DebugMonitor_interrupt
.weak PendingSV_interrupt
.weak SysTick_interrupt
.weak GPIO_Port_A_Interrupt
.weak GPIO_Port_B_Interrupt
.weak GPIO_Port_C_Interrupt
.weak GPIO_Port_D_Interrupt
.weak GPIO_Port_E_Interrupt
.weak UART0_Interrupt
.weak UART1_Interrupt
.weak SSI0_Interrupt
.weak I2C0_Interrupt
.weak ADC0_Sequence_0_Interrupt
.weak ADC0_Sequence_1_Interrupt
.weak ADC0_Sequence_2_Interrupt
.weak ADC0_Sequence_3_Interrupt
.weak Watchdog_Timer_0_Interrupt
.weak Timer_0A_Interrupt
.weak Timer_0B_Interrupt
.weak Timer_1A_Interrupt
.weak Timer_1B_Interrupt
.weak Timer_2A_Interrupt
.weak Timer_2B_Interrupt
.weak Analog_Comparator_0_Interrupt
.weak Analog_Comparator_1_Interrupt
.weak Analog_Comparator_2_Interrupt
.weak System_Control_Interrupt
.weak Flash_Memory_Control_Interrupt
.weak GPIO_Port_F_Interrupt
.weak GPIO_Port_G_Interrupt
.weak GPIO_Port_H_Interrupt
.weak UART2_Interrupt
.weak SSI1_Interrupt
.weak Timer_3A_Interrupt
.weak Timer_3B_Interrupt
.weak I2C1_Interrupt
.weak Hibernation_Module_Interrupt
.set NMI_interrupt, Startup
.set Hardfault_interrupt, Startup
.set MemManage_interrupt, Startup
.set BusFault_interrupt, Startup
.set UsageFault_interrupt, Startup
.set SWI_interrupt, Startup
.set DebugMonitor_interrupt, Startup
.set PendingSV_interrupt, Startup
.set SysTick_interrupt, Startup
.set GPIO_Port_A_Interrupt, Startup
.set GPIO_Port_B_Interrupt, Startup
.set GPIO_Port_C_Interrupt, Startup
.set GPIO_Port_D_Interrupt, Startup
.set GPIO_Port_E_Interrupt, Startup
.set UART0_Interrupt, Startup
.set UART1_Interrupt, Startup
.set SSI0_Interrupt, Startup
.set I2C0_Interrupt, Startup
.set ADC0_Sequence_0_Interrupt, Startup
.set ADC0_Sequence_1_Interrupt, Startup
.set ADC0_Sequence_2_Interrupt, Startup
.set ADC0_Sequence_3_Interrupt, Startup
.set Watchdog_Timer_0_Interrupt, Startup
.set Timer_0A_Interrupt, Startup
.set Timer_0B_Interrupt, Startup
.set Timer_1A_Interrupt, Startup
.set Timer_1B_Interrupt, Startup
.set Timer_2A_Interrupt, Startup
.set Timer_2B_Interrupt, Startup
.set Analog_Comparator_0_Interrupt, Startup
.set Analog_Comparator_1_Interrupt, Startup
.set Analog_Comparator_2_Interrupt, Startup
.set System_Control_Interrupt, Startup
.set Flash_Memory_Control_Interrupt, Startup
.set GPIO_Port_F_Interrupt, Startup
.set GPIO_Port_G_Interrupt, Startup
.set GPIO_Port_H_Interrupt, Startup
.set UART2_Interrupt, Startup
.set SSI1_Interrupt, Startup
.set Timer_3A_Interrupt, Startup
.set Timer_3B_Interrupt, Startup
.set I2C1_Interrupt, Startup
.set Hibernation_Module_Interrupt, Startup
.text
end;
end.

483
rtl/embedded/arm/lm3tempest.pp
View File

@ -60,238 +60,273 @@ unit lm3tempest;
rcgc0 :dword absolute (sysconoffset+$100);
rcgc1 :dword absolute (sysconoffset+$104);
rcgc2 :dword absolute (sysconoffset+$108);
var
NMI_Handler,
HardFault_Handler,
MemManage_Handler,
BusFault_Handler,
UsageFault_Handler,
SWI_Handler,
DebugMonitor_Handler,
PendingSV_Handler,
Systick_Handler,UART0intvector: pointer;
implementation
var
_data: record end; external name '_data';
_edata: record end; external name '_edata';
_etext: record end; external name '_etext';
_bss_start: record end; external name '_bss_start';
_bss_end: record end; external name '_bss_end';
_stack_top: record end; external name '_stack_top';
procedure NMI_interrupt; external name 'NMI_interrupt';
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
procedure MemManage_interrupt; external name 'MemManage_interrupt';
procedure BusFault_interrupt; external name 'BusFault_interrupt';
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
procedure SWI_interrupt; external name 'SWI_interrupt';
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
procedure SysTick_interrupt; external name 'SysTick_interrupt';
procedure GPIO_Port_A_Interrupt; external name 'GPIO_Port_A_Interrupt';
procedure GPIO_Port_B_Interrupt; external name 'GPIO_Port_B_Interrupt';
procedure GPIO_Port_C_Interrupt; external name 'GPIO_Port_C_Interrupt';
procedure GPIO_Port_D_Interrupt; external name 'GPIO_Port_D_Interrupt';
procedure GPIO_Port_E_Interrupt; external name 'GPIO_Port_E_Interrupt';
procedure UART0_Interrupt; external name 'UART0_Interrupt';
procedure UART1_Interrupt; external name 'UART1_Interrupt';
procedure SSI0_Interrupt; external name 'SSI0_Interrupt';
procedure I2C0_Interrupt; external name 'I2C0_Interrupt';
procedure PWM_Fault_Interrupt; external name 'PWM_Fault_Interrupt';
procedure PWM_Generator_0_Interrupt; external name 'PWM_Generator_0_Interrupt';
procedure PWM_Generator_1_Interrupt; external name 'PWM_Generator_1_Interrupt';
procedure PWM_Generator_2_Interrupt; external name 'PWM_Generator_2_Interrupt';
procedure QEI0_Interrupt; external name 'QEI0_Interrupt';
procedure ADC0_Sequence_0_Interrupt; external name 'ADC0_Sequence_0_Interrupt';
procedure ADC0_Sequence_1_Interrupt; external name 'ADC0_Sequence_1_Interrupt';
procedure ADC0_Sequence_2_Interrupt; external name 'ADC0_Sequence_2_Interrupt';
procedure ADC0_Sequence_3_Interrupt; external name 'ADC0_Sequence_3_Interrupt';
procedure Watchdog_Timers_0_and_1_Interrupt; external name 'Watchdog_Timers_0_and_1_Interrupt';
procedure Timer_0A_Interrupt; external name 'Timer_0A_Interrupt';
procedure Timer_0B_Interrupt; external name 'Timer_0B_Interrupt';
procedure Timer_1A_Interrupt; external name 'Timer_1A_Interrupt';
procedure Timer_1B_Interrupt; external name 'Timer_1B_Interrupt';
procedure Timer_2A_Interrupt; external name 'Timer_2A_Interrupt';
procedure Timer_2B_Interrupt; external name 'Timer_2B_Interrupt';
procedure Analog_Comparator_0_Interrupt; external name 'Analog_Comparator_0_Interrupt';
procedure Analog_Comparator_1_Interrupt; external name 'Analog_Comparator_1_Interrupt';
procedure System_Control_Interrupt; external name 'System_Control_Interrupt';
procedure Flash_Memory_Control_Interrupt; external name 'Flash_Memory_Control_Interrupt';
procedure GPIO_Port_F_Interrupt; external name 'GPIO_Port_F_Interrupt';
procedure GPIO_Port_G_Interrupt; external name 'GPIO_Port_G_Interrupt';
procedure GPIO_Port_H_Interrupt; external name 'GPIO_Port_H_Interrupt';
procedure UART2_Interrupt; external name 'UART2_Interrupt';
procedure SSI1_Interrupt; external name 'SSI1_Interrupt';
procedure Timer_3A_Interrupt; external name 'Timer_3A_Interrupt';
procedure Timer_3B_Interrupt; external name 'Timer_3B_Interrupt';
procedure I2C1_Interrupt; external name 'I2C1_Interrupt';
procedure QEI1_Interrupt; external name 'QEI1_Interrupt';
procedure CAN0_Interrupt; external name 'CAN0_Interrupt';
procedure CAN1_Interrupt; external name 'CAN1_Interrupt';
procedure Hibernation_Module_Interrupt; external name 'Hibernation_Module_Interrupt';
procedure USB_Interrupt; external name 'USB_Interrupt';
procedure uDMA_Software_Interrupt; external name 'uDMA_Software_Interrupt';
procedure uDMA_Error_Interrupt; external name 'uDMA_Error_Interrupt';
procedure ADC1_Sequence_0_Interrupt; external name 'ADC1_Sequence_0_Interrupt';
procedure ADC1_Sequence_1_Interrupt; external name 'ADC1_Sequence_1_Interrupt';
procedure ADC1_Sequence_2_Interrupt; external name 'ADC1_Sequence_2_Interrupt';
procedure ADC1_Sequence_3_Interrupt; external name 'ADC1_Sequence_3_Interrupt';
procedure I2S0_Interrupt; external name 'I2S0_Interrupt';
procedure GPIO_Port_J_Interrupt; external name 'GPIO_Port_J_Interrupt';
procedure PASCALMAIN; external name 'PASCALMAIN';
{$i cortexm3_start.inc}
procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
asm
.Lhalt:
b .Lhalt
end;
procedure _FPC_start; assembler; nostackframe;
label
_start;
asm
.init
.align 16
// JEC NOTE: CONFIRMED AUG 2011 - address must manually have offset
// the assembler / linker will NOT automatically add the LSB
// failure to have the LSB prevents coming up in Thumb2 mode
.long _stack_top // First entry in NVIC table is the new stack pointer
.long _start+1 //gjb changed from stm32f version to avoid invstate error when interrupt fires
//b _start // Reset
.long _start+1
//b .LNMI_Addr // Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
.long _start+1
//b .LHardFault_Addr // All class of fault
.long _start+1
//b .LMemManage_Addr // Memory management
.long _start+1
//b .LBusFault_Addr // Pre-fetch fault, memory access fault
.long _start+1
//b .LUsageFault_Addr // Undefined instruction or illegal state
.long _start+1
//nop // Reserved
.long _start+1
//nop // Reserved
.long _start+1
//nop // Reserved
.long _start+1
//nop // Reserved
.long _start+1
//b .LSWI_Addr // Software Interrupt vector now SVC
.long _start+1
//b .LDebugMonitor_Addr // Debug Monitor
.long _start+1
//nop // Reserved
.long _start+1
//b .LPendingSV_Addr // Pendable request for system service
.long _start+1
//b .LSystick_Addr // System tick timer
//16
.long .LDefaultHandler+1 //GPIOA #0
.long .LDefaultHandler+1 //GPIOB
.long .LDefaultHandler+1 //GPIOC
.long .LDefaultHandler+1 //GPIOD
.long .LDefaultHandler+1 //GPIOE
.long .LUART0handler+1 //.LDefaultHandler+1 //UART0
.long .LDefaultHandler+1 //UART1
.long .LDefaultHandler+1 //SSI0
//24
.long .LDefaultHandler+1 //I2C0 #8
.long .LDefaultHandler+1 //PWMF
.long .LDefaultHandler+1 //PWMG0
.long .LDefaultHandler+1 //PWMG1
.long .LDefaultHandler+1 //PWMG2
.long .LDefaultHandler+1 //QEI0
.long .LDefaultHandler+1 //ADC0S0
.long .LDefaultHandler+1 //ADC0S1
//32
.long .LDefaultHandler+1 //ADC0S2 #16
.long .LDefaultHandler+1 //ADC0S3
.long .LDefaultHandler+1 //WDGTimer01
.long .LDefaultHandler+1 //T0A
.long .LDefaultHandler+1 //T0B
.long .LDefaultHandler+1 //T1A
.long .LDefaultHandler+1 //T1B
.long .LDefaultHandler+1 //T2A
//40
.long .LDefaultHandler+1 //T2B #24
.long .LDefaultHandler+1 //COMP0
.long .LDefaultHandler+1 //COMP1
.long .LDefaultHandler+1 //COMP2
.long .LDefaultHandler+1 //SYSCON
.long .LDefaultHandler+1 //FLASH
.long .LDefaultHandler+1 //GPIOF
.long .LDefaultHandler+1 //GPIOG
//48
.long .LDefaultHandler+1 //GPIOH #32
.long .LDefaultHandler+1 //UART2
.long .LDefaultHandler+1 //SSI1
.long .LDefaultHandler+1 //T3A
.long .LDefaultHandler+1 //T3B
.long .LDefaultHandler+1 //I2C1
.long .LDefaultHandler+1 //QEI1
.long .LDefaultHandler+1 //CAN0
//56
.long .LDefaultHandler+1 //CAN1 #40
.long .LDefaultHandler+1 //res
.long .LDefaultHandler+1 //ETH
.long .LDefaultHandler+1 //res
.long .LDefaultHandler+1 //USB
.long .LDefaultHandler+1 //PWMG3
.long .LDefaultHandler+1 //UDMAS
.long .LDefaultHandler+1 //UDMAE
//64
.long .LDefaultHandler+1 //ADC1S0 #48
.long .LDefaultHandler+1 //ADC1S1
.long .LDefaultHandler+1 //ADC1S2
.long .LDefaultHandler+1 //ADC1S3
.long .LDefaultHandler+1 //I2S0
.long .LDefaultHandler+1 //EPI
.long .LDefaultHandler+1 //GPIOJ
.long .LDefaultHandler+1 //res #55
.LNMI_Addr:
ldr r0,.L1
ldr pc,[r0]
.LHardFault_Addr:
ldr r0,.L2
ldr pc,[r0]
.LMemManage_Addr:
ldr r0,.L3
ldr pc,[r0]
.LBusFault_Addr:
ldr r0,.L4
ldr pc,[r0]
.LUsageFault_Addr:
ldr r0,.L5
ldr pc,[r0]
.LSWI_Addr:
ldr r0,.L6
ldr pc,[r0]
.LDebugMonitor_Addr:
ldr r0,.L7
ldr pc,[r0]
.LPendingSV_Addr:
ldr r0,.L8
ldr pc,[r0]
.LSystick_Addr:
ldr r0,.L9
ldr pc,[r0]
.LUART0handler:
ldr r0,.L10
ldr pc,[r0]
.L1:
.long NMI_Handler
.L2:
.long HardFault_Handler
.L3:
.long MemManage_Handler
.L4:
.long BusFault_Handler
.L5:
.long UsageFault_Handler
.L6:
.long SWI_Handler
.L7:
.long DebugMonitor_Handler
.L8:
.long PendingSV_Handler
.L9:
.long Systick_Handler
.L10:
.long UART0IntVector
procedure Vectors; assembler; nostackframe;
label interrupt_vectors;
asm
.section ".init.interrupt_vectors"
interrupt_vectors:
.long _stack_top
.long Startup
.long NMI_interrupt
.long Hardfault_interrupt
.long MemManage_interrupt
.long BusFault_interrupt
.long UsageFault_interrupt
.long 0
.long 0
.long 0
.long 0
.long SWI_interrupt
.long DebugMonitor_interrupt
.long 0
.long PendingSV_interrupt
.long SysTick_interrupt
.globl _start
.text
_start:
// Copy initialized data to ram
ldr r1,.L_etext
ldr r2,.L_data
ldr r3,.L_edata
.Lcopyloop:
cmp r2,r3
ittt ls
ldrls r0,[r1],#4
strls r0,[r2],#4
bls .Lcopyloop
.long GPIO_Port_A_Interrupt
.long GPIO_Port_B_Interrupt
.long GPIO_Port_C_Interrupt
.long GPIO_Port_D_Interrupt
.long GPIO_Port_E_Interrupt
.long UART0_Interrupt
.long UART1_Interrupt
.long SSI0_Interrupt
.long I2C0_Interrupt
.long PWM_Fault_Interrupt
.long PWM_Generator_0_Interrupt
.long PWM_Generator_1_Interrupt
.long PWM_Generator_2_Interrupt
.long QEI0_Interrupt
.long ADC0_Sequence_0_Interrupt
.long ADC0_Sequence_1_Interrupt
.long ADC0_Sequence_2_Interrupt
.long ADC0_Sequence_3_Interrupt
.long Watchdog_Timers_0_and_1_Interrupt
.long Timer_0A_Interrupt
.long Timer_0B_Interrupt
.long Timer_1A_Interrupt
.long Timer_1B_Interrupt
.long Timer_2A_Interrupt
.long Timer_2B_Interrupt
.long Analog_Comparator_0_Interrupt
.long Analog_Comparator_1_Interrupt
.long 0
.long System_Control_Interrupt
.long Flash_Memory_Control_Interrupt
.long GPIO_Port_F_Interrupt
.long GPIO_Port_G_Interrupt
.long GPIO_Port_H_Interrupt
.long UART2_Interrupt
.long SSI1_Interrupt
.long Timer_3A_Interrupt
.long Timer_3B_Interrupt
.long I2C1_Interrupt
.long QEI1_Interrupt
.long CAN0_Interrupt
.long CAN1_Interrupt
.long 0
.long 0
.long Hibernation_Module_Interrupt
.long USB_Interrupt
.long 0
.long uDMA_Software_Interrupt
.long uDMA_Error_Interrupt
.long ADC1_Sequence_0_Interrupt
.long ADC1_Sequence_1_Interrupt
.long ADC1_Sequence_2_Interrupt
.long ADC1_Sequence_3_Interrupt
.long I2S0_Interrupt
.long 0
.long GPIO_Port_J_Interrupt
.weak NMI_interrupt
.weak Hardfault_interrupt
.weak MemManage_interrupt
.weak BusFault_interrupt
.weak UsageFault_interrupt
.weak SWI_interrupt
.weak DebugMonitor_interrupt
.weak PendingSV_interrupt
.weak SysTick_interrupt
// clear onboard ram
ldr r1,.L_bss_start
ldr r2,.L_bss_end
mov r0,#0
.Lzeroloop:
cmp r1,r2
itt ls
strls r0,[r1],#4
bls .Lzeroloop
.weak GPIO_Port_A_Interrupt
.weak GPIO_Port_B_Interrupt
.weak GPIO_Port_C_Interrupt
.weak GPIO_Port_D_Interrupt
.weak GPIO_Port_E_Interrupt
.weak UART0_Interrupt
.weak UART1_Interrupt
.weak SSI0_Interrupt
.weak I2C0_Interrupt
.weak PWM_Fault_Interrupt
.weak PWM_Generator_0_Interrupt
.weak PWM_Generator_1_Interrupt
.weak PWM_Generator_2_Interrupt
.weak QEI0_Interrupt
.weak ADC0_Sequence_0_Interrupt
.weak ADC0_Sequence_1_Interrupt
.weak ADC0_Sequence_2_Interrupt
.weak ADC0_Sequence_3_Interrupt
.weak Watchdog_Timers_0_and_1_Interrupt
.weak Timer_0A_Interrupt
.weak Timer_0B_Interrupt
.weak Timer_1A_Interrupt
.weak Timer_1B_Interrupt
.weak Timer_2A_Interrupt
.weak Timer_2B_Interrupt
.weak Analog_Comparator_0_Interrupt
.weak Analog_Comparator_1_Interrupt
.weak System_Control_Interrupt
.weak Flash_Memory_Control_Interrupt
.weak GPIO_Port_F_Interrupt
.weak GPIO_Port_G_Interrupt
.weak GPIO_Port_H_Interrupt
.weak UART2_Interrupt
.weak SSI1_Interrupt
.weak Timer_3A_Interrupt
.weak Timer_3B_Interrupt
.weak I2C1_Interrupt
.weak QEI1_Interrupt
.weak CAN0_Interrupt
.weak CAN1_Interrupt
.weak Hibernation_Module_Interrupt
.weak USB_Interrupt
.weak uDMA_Software_Interrupt
.weak uDMA_Error_Interrupt
.weak ADC1_Sequence_0_Interrupt
.weak ADC1_Sequence_1_Interrupt
.weak ADC1_Sequence_2_Interrupt
.weak ADC1_Sequence_3_Interrupt
.weak I2S0_Interrupt
.weak GPIO_Port_J_Interrupt
.set NMI_interrupt, Startup
.set Hardfault_interrupt, Startup
.set MemManage_interrupt, Startup
.set BusFault_interrupt, Startup
.set UsageFault_interrupt, Startup
.set SWI_interrupt, Startup
.set DebugMonitor_interrupt, Startup
.set PendingSV_interrupt, Startup
.set SysTick_interrupt, Startup
b PASCALMAIN
b _FPC_haltproc
.L_bss_start:
.long _bss_start
.L_bss_end:
.long _bss_end
.L_etext:
.long _etext
.L_data:
.long _data
.L_edata:
.long _edata
.LDefaultHandlerAddr:
.long .LDefaultHandler
// default irq handler just returns
.LDefaultHandler:
mov pc,r14
end;
.set GPIO_Port_A_Interrupt, Startup
.set GPIO_Port_B_Interrupt, Startup
.set GPIO_Port_C_Interrupt, Startup
.set GPIO_Port_D_Interrupt, Startup
.set GPIO_Port_E_Interrupt, Startup
.set UART0_Interrupt, Startup
.set UART1_Interrupt, Startup
.set SSI0_Interrupt, Startup
.set I2C0_Interrupt, Startup
.set PWM_Fault_Interrupt, Startup
.set PWM_Generator_0_Interrupt, Startup
.set PWM_Generator_1_Interrupt, Startup
.set PWM_Generator_2_Interrupt, Startup
.set QEI0_Interrupt, Startup
.set ADC0_Sequence_0_Interrupt, Startup
.set ADC0_Sequence_1_Interrupt, Startup
.set ADC0_Sequence_2_Interrupt, Startup
.set ADC0_Sequence_3_Interrupt, Startup
.set Watchdog_Timers_0_and_1_Interrupt, Startup
.set Timer_0A_Interrupt, Startup
.set Timer_0B_Interrupt, Startup
.set Timer_1A_Interrupt, Startup
.set Timer_1B_Interrupt, Startup
.set Timer_2A_Interrupt, Startup
.set Timer_2B_Interrupt, Startup
.set Analog_Comparator_0_Interrupt, Startup
.set Analog_Comparator_1_Interrupt, Startup
.set System_Control_Interrupt, Startup
.set Flash_Memory_Control_Interrupt, Startup
.set GPIO_Port_F_Interrupt, Startup
.set GPIO_Port_G_Interrupt, Startup
.set GPIO_Port_H_Interrupt, Startup
.set UART2_Interrupt, Startup
.set SSI1_Interrupt, Startup
.set Timer_3A_Interrupt, Startup
.set Timer_3B_Interrupt, Startup
.set I2C1_Interrupt, Startup
.set QEI1_Interrupt, Startup
.set CAN0_Interrupt, Startup
.set CAN1_Interrupt, Startup
.set Hibernation_Module_Interrupt, Startup
.set USB_Interrupt, Startup
.set uDMA_Software_Interrupt, Startup
.set uDMA_Error_Interrupt, Startup
.set ADC1_Sequence_0_Interrupt, Startup
.set ADC1_Sequence_1_Interrupt, Startup
.set ADC1_Sequence_2_Interrupt, Startup
.set ADC1_Sequence_3_Interrupt, Startup
.set I2S0_Interrupt, Startup
.set GPIO_Port_J_Interrupt, Startup
.text
end;
end.

318
rtl/embedded/arm/lpc1768.pp
View File

@ -25,134 +25,202 @@ var
implementation
var
_data: record end; external name '_data';
_edata: record end; external name '_edata';
_etext: record end; external name '_etext';
_bss_start: record end; external name '_bss_start';
_bss_end: record end; external name '_bss_end';
_stack_top: record end; external name '_stack_top';
procedure NMI_interrupt; external name 'NMI_interrupt';
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
procedure MemManage_interrupt; external name 'MemManage_interrupt';
procedure BusFault_interrupt; external name 'BusFault_interrupt';
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
procedure SWI_interrupt; external name 'SWI_interrupt';
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
procedure SysTick_interrupt; external name 'SysTick_interrupt';
procedure Watchdog_Interrupt; external name 'Watchdog_Interrupt';
procedure Timer0_Interrupt; external name 'Timer0_Interrupt';
procedure Timer1_Interrupt; external name 'Timer1_Interrupt';
procedure Timer2_Interrupt; external name 'Timer2_Interrupt';
procedure Timer3_Interrupt; external name 'Timer3_Interrupt';
procedure UART0_Interrupt; external name 'UART0_Interrupt';
procedure UART1_Interrupt; external name 'UART1_Interrupt';
procedure UART2_Interrupt; external name 'UART2_Interrupt';
procedure UART3_Interrupt; external name 'UART3_Interrupt';
procedure PWM1_Interrupt; external name 'PWM1_Interrupt';
procedure I2C0_Interrupt; external name 'I2C0_Interrupt';
procedure I2C1_Interrupt; external name 'I2C1_Interrupt';
procedure I2C2_Interrupt; external name 'I2C2_Interrupt';
procedure SPI_Interrupt; external name 'SPI_Interrupt';
procedure SSP0_Interrupt; external name 'SSP0_Interrupt';
procedure SSP1_Interrupt; external name 'SSP1_Interrupt';
procedure PLL0_Interrupt; external name 'PLL0_Interrupt';
procedure RTC_Interrupt; external name 'RTC_Interrupt';
procedure EINT0_Interrupt; external name 'EINT0_Interrupt';
procedure EINT1_Interrupt; external name 'EINT1_Interrupt';
procedure EINT2_Interrupt; external name 'EINT2_Interrupt';
procedure EINT3_Interrupt; external name 'EINT3_Interrupt';
procedure ADC_Interrupt; external name 'ADC_Interrupt';
procedure BOD_Interrupt; external name 'BOD_Interrupt';
procedure USB_Interrupt; external name 'USB_Interrupt';
procedure CAN_Interrupt; external name 'CAN_Interrupt';
procedure HPDMA_Interrupt; external name 'HPDMA_Interrupt';
procedure I2C_Interrupt; external name 'I2C_Interrupt';
procedure Ethernet_Interrupt; external name 'Ethernet_Interrupt';
procedure RITINT_Interrupt; external name 'RITINT_Interrupt';
procedure MotorControlPWM_Interrupt; external name 'MotorControlPWM_Interrupt';
procedure QuadratureEncoder_Interrupt; external name 'QuadratureEncoder_Interrupt';
procedure PLL1_Interrupt; external name 'PLL1_Interrupt';
procedure USBActivity_Interrupt; external name 'USBActivity_Interrupt';
procedure CanActivity_Interrupt; external name 'CanActivity_Interrupt';
procedure PASCALMAIN; external name 'PASCALMAIN';
{$i cortexm3_start.inc}
procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
procedure Vectors; assembler; nostackframe;
label interrupt_vectors;
asm
.Lhalt:
b .Lhalt
end;
procedure _FPC_start; assembler; nostackframe;
label _start;
asm
.init
.balign 16
.long _stack_top // stack top address
.long _start+1 // 1 Reset
.long .LDefaultHandler+1 // 2 NMI
.long .LDefaultHandler+1 // 3 HardFault
.long .LDefaultHandler+1 // 4 MemManage
.long .LDefaultHandler+1 // 5 BusFault
.long .LDefaultHandler+1 // 6 UsageFault
.long .LDefaultHandler+1 // 7 RESERVED
.long .LDefaultHandler+1 // 8 RESERVED
.long .LDefaultHandler+1 // 9 RESERVED
.long .LDefaultHandler+1 // 10 RESERVED
.long .LDefaultHandler+1 // 11 SVCall
.long .LDefaultHandler+1 // 12 Debug Monitor
.long .LDefaultHandler+1 // 13 RESERVED
.long .LDefaultHandler+1 // 14 PendSV
.long .LDefaultHandler+1 // 15 SysTick
.long .LDefaultHandler+1 // 16 External Interrupt(0)
.long .LDefaultHandler+1 // 17 External Interrupt(1)
.long .LDefaultHandler+1 // 18 External Interrupt(2)
.long .LDefaultHandler+1 // 19 ...
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.globl _start
.text
_start:
// Copy initialized data to ram
ldr r1,.L_etext
ldr r2,.L_data
ldr r3,.L_edata
.Lcopyloop:
cmp r2,r3
ittt ls
ldrls r0,[r1],#4
strls r0,[r2],#4
bls .Lcopyloop
// clear onboard ram
ldr r1,.L_bss_start
ldr r2,.L_bss_end
mov r0,#0
.Lzeroloop:
cmp r1,r2
itt ls
strls r0,[r1],#4
bls .Lzeroloop
b PASCALMAIN
b _FPC_haltproc
.L_bss_start:
.long _bss_start
.L_bss_end:
.long _bss_end
.L_etext:
.long _etext
.L_data:
.long _data
.L_edata:
.long _edata
.LDefaultHandlerAddr:
.long .LDefaultHandler
// default irq handler just returns
.LDefaultHandler:
mov pc,r14
.section ".init.interrupt_vectors"
interrupt_vectors:
.long _stack_top // stack top address
.long Startup
.long NMI_interrupt
.long Hardfault_interrupt
.long MemManage_interrupt
.long BusFault_interrupt
.long UsageFault_interrupt
.long 0
.long 0
.long 0
.long 0
.long SWI_interrupt
.long DebugMonitor_interrupt
.long 0
.long PendingSV_interrupt
.long SysTick_interrupt
.long Watchdog_Interrupt
.long Timer0_Interrupt
.long Timer1_Interrupt
.long Timer2_Interrupt
.long Timer3_Interrupt
.long UART0_Interrupt
.long UART1_Interrupt
.long UART2_Interrupt
.long UART3_Interrupt
.long PWM1_Interrupt
.long I2C0_Interrupt
.long I2C1_Interrupt
.long I2C2_Interrupt
.long SPI_Interrupt
.long SSP0_Interrupt
.long SSP1_Interrupt
.long PLL0_Interrupt
.long RTC_Interrupt
.long EINT0_Interrupt
.long EINT1_Interrupt
.long EINT2_Interrupt
.long EINT3_Interrupt
.long ADC_Interrupt
.long BOD_Interrupt
.long USB_Interrupt
.long CAN_Interrupt
.long HPDMA_Interrupt
.long I2C_Interrupt
.long Ethernet_Interrupt
.long RITINT_Interrupt
.long MotorControlPWM_Interrupt
.long QuadratureEncoder_Interrupt
.long PLL1_Interrupt
.long USBActivity_Interrupt
.long CanActivity_Interrupt
.weak NMI_interrupt
.weak Hardfault_interrupt
.weak MemManage_interrupt
.weak BusFault_interrupt
.weak UsageFault_interrupt
.weak SWI_interrupt
.weak DebugMonitor_interrupt
.weak PendingSV_interrupt
.weak SysTick_interrupt
.weak Watchdog_Interrupt
.weak Timer0_Interrupt
.weak Timer1_Interrupt
.weak Timer2_Interrupt
.weak Timer3_Interrupt
.weak UART0_Interrupt
.weak UART1_Interrupt
.weak UART2_Interrupt
.weak UART3_Interrupt
.weak PWM1_Interrupt
.weak I2C0_Interrupt
.weak I2C1_Interrupt
.weak I2C2_Interrupt
.weak SPI_Interrupt
.weak SSP0_Interrupt
.weak SSP1_Interrupt
.weak PLL0_Interrupt
.weak RTC_Interrupt
.weak EINT0_Interrupt
.weak EINT1_Interrupt
.weak EINT2_Interrupt
.weak EINT3_Interrupt
.weak ADC_Interrupt
.weak BOD_Interrupt
.weak USB_Interrupt
.weak CAN_Interrupt
.weak HPDMA_Interrupt
.weak I2C_Interrupt
.weak Ethernet_Interrupt
.weak RITINT_Interrupt
.weak MotorControlPWM_Interrupt
.weak QuadratureEncoder_Interrupt
.weak PLL1_Interrupt
.weak USBActivity_Interrupt
.weak CanActivity_Interrupt
.set NMI_interrupt, Startup
.set Hardfault_interrupt, Startup
.set MemManage_interrupt, Startup
.set BusFault_interrupt, Startup
.set UsageFault_interrupt, Startup
.set SWI_interrupt, Startup
.set DebugMonitor_interrupt, Startup
.set PendingSV_interrupt, Startup
.set SysTick_interrupt, Startup
.set Watchdog_Interrupt, Startup
.set Timer0_Interrupt, Startup
.set Timer1_Interrupt, Startup
.set Timer2_Interrupt, Startup
.set Timer3_Interrupt, Startup
.set UART0_Interrupt, Startup
.set UART1_Interrupt, Startup
.set UART2_Interrupt, Startup
.set UART3_Interrupt, Startup
.set PWM1_Interrupt, Startup
.set I2C0_Interrupt, Startup
.set I2C1_Interrupt, Startup
.set I2C2_Interrupt, Startup
.set SPI_Interrupt, Startup
.set SSP0_Interrupt, Startup
.set SSP1_Interrupt, Startup
.set PLL0_Interrupt, Startup
.set RTC_Interrupt, Startup
.set EINT0_Interrupt, Startup
.set EINT1_Interrupt, Startup
.set EINT2_Interrupt, Startup
.set EINT3_Interrupt, Startup
.set ADC_Interrupt, Startup
.set BOD_Interrupt, Startup
.set USB_Interrupt, Startup
.set CAN_Interrupt, Startup
.set HPDMA_Interrupt, Startup
.set I2C_Interrupt, Startup
.set Ethernet_Interrupt, Startup
.set RITINT_Interrupt, Startup
.set MotorControlPWM_Interrupt, Startup
.set QuadratureEncoder_Interrupt, Startup
.set PLL1_Interrupt, Startup
.set USBActivity_Interrupt, Startup
.set CanActivity_Interrupt, Startup
.text
end;
end.

632
rtl/embedded/arm/sc32442b.pp
View File

@ -8,7 +8,7 @@ unit sc32442b;
interface
var
{ Memory Controller }
{ Memory Controller }
BWSCON: longword absolute $48000000;
BANKCON0: longword absolute $48000004;
BANKCON1: longword absolute $48000008;
@ -21,8 +21,8 @@ unit sc32442b;
REFRESH: longword absolute $48000024;
BANKSIZE: longword absolute $48000028;
MRSRB6: longword absolute $4800002C;
{ USB Host Controller }
{ USB Host Controller }
HcRevision: longword absolute $49000000;
HcControl: longword absolute $49000004;
HcCommonStatus: longword absolute $49000008;
@ -46,8 +46,8 @@ unit sc32442b;
HcRhStatus: longword absolute $49000050;
HcRhPortStatus1: longword absolute $49000054;
HcRhPortStatus2: longword absolute $49000058;
{ Interrupt controller }
{ Interrupt controller }
SRCPND: longword absolute $4A000000;
INTMOD: longword absolute $4A000004;
INTMSK: longword absolute $4A000008;
@ -56,291 +56,278 @@ unit sc32442b;
INTOFFSET: longword absolute $4A000014;
SUBSRCPND: longword absolute $4A000018;
INTSUBMSK: longword absolute $4A00001C;
type
TDMA = packed record
DISRC,
DISRCC,
DIDST,
DIDSTC,
DCON,
DSTAT,
DCSRC,
DCDST,
DMASKTRIG: longword;
end;
var
{ DMA }
DMA0: TDMA absolute $4B000000;
DMA1: TDMA absolute $4B000040;
DMA2: TDMA absolute $4B000080;
DMA3: TDMA absolute $4B0000C0;
{ Clock and power }
LOCKTIME: longword absolute $4C000000;
MPLLCON: longword absolute $4C000004;
UPLLCON: longword absolute $4C000008;
CLKCON: longword absolute $4C00000C;
CLKSLOW: longword absolute $4C000010;
CLKDIVN: longword absolute $4C000014;
CAMDIVN: longword absolute $4C000018;
{ LCD Controller }
LCDCON1: longword absolute $4D000000;
LCDCON2: longword absolute $4D000004;
LCDCON3: longword absolute $4D000008;
LCDCON4: longword absolute $4D00000C;
LCDCON5: longword absolute $4D000010;
LCDSADDR1: longword absolute $4D000014;
LCDSADDR2: longword absolute $4D000018;
LCDSADDR3: longword absolute $4D00001C;
REDLUT: longword absolute $4D000020;
GREENLUT: longword absolute $4D000024;
BLUELUT: longword absolute $4D000028;
DITHMODE: longword absolute $4D00004C;
TPAL: longword absolute $4D000050;
LCDINTPND: longword absolute $4D000054;
LCDSRCPND: longword absolute $4D000058;
LCDINTMSK: longword absolute $4D00005C;
TCONSEL: longword absolute $4D000060;
{ NAND Flash }
NFCONF: longword absolute $4E000000;
NFCONT: longword absolute $4E000004;
NFCMD: longword absolute $4E000008;
NFADDR: longword absolute $4E00000C;
NFDATA: longword absolute $4E000010;
NFECC0: longword absolute $4E000014;
NFECC1: longword absolute $4E000018;
NFSECC: longword absolute $4E00001C;
NFSTAT: longword absolute $4E000020;
NFESTAT0: longword absolute $4E000024;
NFESTAT1: longword absolute $4E000028;
NFMECC0: longword absolute $4E00002C;
NFMECC1: longword absolute $4E000030;
NFSECC2: longword absolute $4E000034;
NFSBLK: longword absolute $4E000038;
NFEBLK: longword absolute $4E00003C;
TDMA = packed record
DISRC,
DISRCC,
DIDST,
DIDSTC,
DCON,
DSTAT,
DCSRC,
DCDST,
DMASKTRIG: longword;
end;
var
{ DMA }
DMA0: TDMA absolute $4B000000;
DMA1: TDMA absolute $4B000040;
DMA2: TDMA absolute $4B000080;
DMA3: TDMA absolute $4B0000C0;
{ Clock and power }
LOCKTIME: longword absolute $4C000000;
MPLLCON: longword absolute $4C000004;
UPLLCON: longword absolute $4C000008;
CLKCON: longword absolute $4C00000C;
CLKSLOW: longword absolute $4C000010;
CLKDIVN: longword absolute $4C000014;
CAMDIVN: longword absolute $4C000018;
{ LCD Controller }
LCDCON1: longword absolute $4D000000;
LCDCON2: longword absolute $4D000004;
LCDCON3: longword absolute $4D000008;
LCDCON4: longword absolute $4D00000C;
LCDCON5: longword absolute $4D000010;
LCDSADDR1: longword absolute $4D000014;
LCDSADDR2: longword absolute $4D000018;
LCDSADDR3: longword absolute $4D00001C;
REDLUT: longword absolute $4D000020;
GREENLUT: longword absolute $4D000024;
BLUELUT: longword absolute $4D000028;
DITHMODE: longword absolute $4D00004C;
TPAL: longword absolute $4D000050;
LCDINTPND: longword absolute $4D000054;
LCDSRCPND: longword absolute $4D000058;
LCDINTMSK: longword absolute $4D00005C;
TCONSEL: longword absolute $4D000060;
{ NAND Flash }
NFCONF: longword absolute $4E000000;
NFCONT: longword absolute $4E000004;
NFCMD: longword absolute $4E000008;
NFADDR: longword absolute $4E00000C;
NFDATA: longword absolute $4E000010;
NFECC0: longword absolute $4E000014;
NFECC1: longword absolute $4E000018;
NFSECC: longword absolute $4E00001C;
NFSTAT: longword absolute $4E000020;
NFESTAT0: longword absolute $4E000024;
NFESTAT1: longword absolute $4E000028;
NFMECC0: longword absolute $4E00002C;
NFMECC1: longword absolute $4E000030;
NFSECC2: longword absolute $4E000034;
NFSBLK: longword absolute $4E000038;
NFEBLK: longword absolute $4E00003C;
type
TUART = packed record
ULCON,
UCON,
UFCON,
UMCON,
UTRSTAT,
UERSTAT,
UFSTAT,
UMSTAT,
UTXH,
URXH,
UBRDIV: longword;
end;
var
{ UART }
UART0: TUART absolute $50000000;
UART1: TUART absolute $50004000;
UART2: TUART absolute $50008000;
type
TPWMTimer = packed record
TCNTB,
TCMPB,
TCNTO: longword;
end;
var
{ PWM Timer }
TCFG0: longword absolute $51000000;
TCFG1: longword absolute $51000004;
TCON: longword absolute $51000008;
PWMTimer: array[0..4] of TPWMTimer absolute $5100000C;
{ USB Device }
FUNC_ADDR_REG: byte absolute $52000140;
PWR_REG: byte absolute $52000144;
EP_INT_REG: byte absolute $52000148;
USB_INT_REG: byte absolute $52000158;
EP_INT_EN_REG: byte absolute $5200015C;
USB_INT_EN_REG: byte absolute $5200016C;
FRAME_NUM1_REG: byte absolute $52000170;
FRAME_NUM2_REG: byte absolute $52000174;
INDEX_REG: byte absolute $52000178;
EP0_CSR: byte absolute $52000184;
IN_CSR1_REG: byte absolute $52000184;
IN_CSR2_REG: byte absolute $52000188;
MAXP_REG: byte absolute $52000180;
OUT_CSR1_REG: byte absolute $52000190;
OUT_CSR2_REG: byte absolute $52000194;
OUT_FIFO_CNT1_REG: byte absolute $52000198;
OUT_FIFO_CNT2_REG: byte absolute $5200019C;
EP0_FIFO: byte absolute $520001C0;
EP1_FIFO: byte absolute $520001C4;
EP2_FIFO: byte absolute $520001C8;
EP3_FIFO: byte absolute $520001CC;
EP4_FIFO: byte absolute $520001D0;
EP1_DMA_CON: byte absolute $52000200;
EP1_DMA_UNIT: byte absolute $52000204;
EP1_DMA_FIFO: byte absolute $52000208;
EP1_DMA_TTC_L: byte absolute $5200020C;
EP1_DMA_TTC_M: byte absolute $52000210;
EP1_DMA_TTC_H: byte absolute $52000214;
EP2_DMA_CON: byte absolute $52000218;
EP2_DMA_UNIT: byte absolute $5200021C;
EP2_DMA_FIFO: byte absolute $52000220;
EP2_DMA_TTC_L: byte absolute $52000224;
EP2_DMA_TTC_M: byte absolute $52000228;
EP2_DMA_TTC_H: byte absolute $5200022C;
EP3_DMA_CON: byte absolute $52000240;
EP3_DMA_UNIT: byte absolute $52000244;
EP3_DMA_FIFO: byte absolute $52000248;
EP3_DMA_TTC_L: byte absolute $5200024C;
EP3_DMA_TTC_M: byte absolute $52000250;
EP3_DMA_TTC_H: byte absolute $52000254;
EP4_DMA_CON: byte absolute $52000258;
EP4_DMA_UNIT: byte absolute $5200025C;
EP4_DMA_FIFO: byte absolute $52000260;
EP4_DMA_TTC_L: byte absolute $52000264;
EP4_DMA_TTC_M: byte absolute $52000268;
EP4_DMA_TTC_H: byte absolute $5200026C;
{ Watchdog timer }
WTCON: longword absolute $53000000;
WTDAT: longword absolute $53000004;
WTCNT: longword absolute $53000008;
{ I2C }
IICCON: longword absolute $54000000;
IICSTAT: longword absolute $54000004;
IICADD: longword absolute $54000008;
IICDS: longword absolute $5400000C;
IICLC: longword absolute $54000010;
{ I2S }
IISCON: longword absolute $55000000;
IISMOD: longword absolute $55000004;
IISPSR: longword absolute $55000008;
IISFCON: longword absolute $5500000C;
IISFIFO: longword absolute $55000010;
type
TGPIO = packed record
CON,
DAT,
DN: longword;
end;
var
{ GPIO }
GPA: TGPIO absolute $56000000;
GPB: TGPIO absolute $56000010;
GPC: TGPIO absolute $56000020;
GPD: TGPIO absolute $56000030;
GPE: TGPIO absolute $56000040;
GPF: TGPIO absolute $56000050;
GPG: TGPIO absolute $56000060;
GPH: TGPIO absolute $56000070;
GPJ: TGPIO absolute $560000D0;
MISCCR: longword absolute $56000080;
DCLKCON: longword absolute $56000084;
EXTINT0: longword absolute $56000088;
EXTINT1: longword absolute $5600008C;
EXTINT2: longword absolute $56000090;
EINTFLT0: longword absolute $56000094;
EINTFLT1: longword absolute $56000098;
EINTFLT2: longword absolute $5600009C;
EINTFLT3: longword absolute $560000A0;
EINTMASK: longword absolute $560000A4;
EINTPEND: longword absolute $560000A8;
GSTATUS0: longword absolute $560000AC;
GSTATUS1: longword absolute $560000B0;
GSTATUS2: longword absolute $560000B4;
GSTATUS3: longword absolute $560000B8;
GSTATUS4: longword absolute $560000BC;
MSLCON: longword absolute $560000CC;
{ RTC }
RTCCON: byte absolute $57000040;
TICNT: byte absolute $57000044;
RTCALM: byte absolute $57000050;
ALMSEC: byte absolute $57000054;
ALMMIN: byte absolute $57000058;
ALMHOUR: byte absolute $5700005C;
ALMDATE: byte absolute $57000060;
ALMMON: byte absolute $57000064;
ALMYEAR: byte absolute $57000068;
BCDSEC: byte absolute $57000070;
BCDMIN: byte absolute $57000074;
BCDHOUR: byte absolute $57000078;
BCDDATE: byte absolute $5700007C;
BCDDAY: byte absolute $57000080;
BCDMON: byte absolute $57000084;
BCDYEAR: byte absolute $57000088;
RTCLBAT: byte absolute $5700006C;
{ AD converter }
ADCCON: longword absolute $58000000;
ADCTSC: longword absolute $58000004;
ADCDLY: longword absolute $58000008;
ADCDAT0: longword absolute $5800000C;
ADCDAT1: longword absolute $58000010;
ADCUPDN: longword absolute $58000014;
type
TSPI = packed record
SPCON,
SPSTA,
SPPIN,
SPPRE,
SPTDAT,
SPRDAT: longword;
end;
var
{ SPI }
SPI0: TSPI absolute $59000000;
SPI1: TSPI absolute $59000020;
{ SD Interface }
SDICON: longword absolute $5A000000;
SDIPRE: longword absolute $5A000004;
SDICARG: longword absolute $5A000008;
SDICCON: longword absolute $5A00000C;
SDICSTA: longword absolute $5A000010;
SDIRSP0: longword absolute $5A000014;
SDIRSP1: longword absolute $5A000018;
SDIRSP2: longword absolute $5A00001C;
SDIRSP3: longword absolute $5A000020;
SDIDTIMER: longword absolute $5A000024;
SDIBSIZE: longword absolute $5A000028;
SDIDCON: longword absolute $5A00002C;
SDIDCNT: longword absolute $5A000030;
SDIDSTA: longword absolute $5A000034;
SDIFSTA: longword absolute $5A000038;
SDIIMSK: longword absolute $5A00003C;
SDIDAT: byte absolute $5A000040;
var
Undefined_Handler,
SWI_Handler,
Prefetch_Handler,
Abort_Handler,
IRQ_Handler,
FIQ_Handler : pointer;
TUART = packed record
ULCON,
UCON,
UFCON,
UMCON,
UTRSTAT,
UERSTAT,
UFSTAT,
UMSTAT,
UTXH,
URXH,
UBRDIV: longword;
end;
var
{ UART }
UART0: TUART absolute $50000000;
UART1: TUART absolute $50004000;
UART2: TUART absolute $50008000;
type
TPWMTimer = packed record
TCNTB,
TCMPB,
TCNTO: longword;
end;
var
{ PWM Timer }
TCFG0: longword absolute $51000000;
TCFG1: longword absolute $51000004;
TCON: longword absolute $51000008;
PWMTimer: array[0..4] of TPWMTimer absolute $5100000C;
{ USB Device }
FUNC_ADDR_REG: byte absolute $52000140;
PWR_REG: byte absolute $52000144;
EP_INT_REG: byte absolute $52000148;
USB_INT_REG: byte absolute $52000158;
EP_INT_EN_REG: byte absolute $5200015C;
USB_INT_EN_REG: byte absolute $5200016C;
FRAME_NUM1_REG: byte absolute $52000170;
FRAME_NUM2_REG: byte absolute $52000174;
INDEX_REG: byte absolute $52000178;
EP0_CSR: byte absolute $52000184;
IN_CSR1_REG: byte absolute $52000184;
IN_CSR2_REG: byte absolute $52000188;
MAXP_REG: byte absolute $52000180;
OUT_CSR1_REG: byte absolute $52000190;
OUT_CSR2_REG: byte absolute $52000194;
OUT_FIFO_CNT1_REG: byte absolute $52000198;
OUT_FIFO_CNT2_REG: byte absolute $5200019C;
EP0_FIFO: byte absolute $520001C0;
EP1_FIFO: byte absolute $520001C4;
EP2_FIFO: byte absolute $520001C8;
EP3_FIFO: byte absolute $520001CC;
EP4_FIFO: byte absolute $520001D0;
EP1_DMA_CON: byte absolute $52000200;
EP1_DMA_UNIT: byte absolute $52000204;
EP1_DMA_FIFO: byte absolute $52000208;
EP1_DMA_TTC_L: byte absolute $5200020C;
EP1_DMA_TTC_M: byte absolute $52000210;
EP1_DMA_TTC_H: byte absolute $52000214;
EP2_DMA_CON: byte absolute $52000218;
EP2_DMA_UNIT: byte absolute $5200021C;
EP2_DMA_FIFO: byte absolute $52000220;
EP2_DMA_TTC_L: byte absolute $52000224;
EP2_DMA_TTC_M: byte absolute $52000228;
EP2_DMA_TTC_H: byte absolute $5200022C;
EP3_DMA_CON: byte absolute $52000240;
EP3_DMA_UNIT: byte absolute $52000244;
EP3_DMA_FIFO: byte absolute $52000248;
EP3_DMA_TTC_L: byte absolute $5200024C;
EP3_DMA_TTC_M: byte absolute $52000250;
EP3_DMA_TTC_H: byte absolute $52000254;
EP4_DMA_CON: byte absolute $52000258;
EP4_DMA_UNIT: byte absolute $5200025C;
EP4_DMA_FIFO: byte absolute $52000260;
EP4_DMA_TTC_L: byte absolute $52000264;
EP4_DMA_TTC_M: byte absolute $52000268;
EP4_DMA_TTC_H: byte absolute $5200026C;
{ Watchdog timer }
WTCON: longword absolute $53000000;
WTDAT: longword absolute $53000004;
WTCNT: longword absolute $53000008;
{ I2C }
IICCON: longword absolute $54000000;
IICSTAT: longword absolute $54000004;
IICADD: longword absolute $54000008;
IICDS: longword absolute $5400000C;
IICLC: longword absolute $54000010;
{ I2S }
IISCON: longword absolute $55000000;
IISMOD: longword absolute $55000004;
IISPSR: longword absolute $55000008;
IISFCON: longword absolute $5500000C;
IISFIFO: longword absolute $55000010;
type
TGPIO = packed record
CON,
DAT,
DN: longword;
end;
var
{ GPIO }
GPA: TGPIO absolute $56000000;
GPB: TGPIO absolute $56000010;
GPC: TGPIO absolute $56000020;
GPD: TGPIO absolute $56000030;
GPE: TGPIO absolute $56000040;
GPF: TGPIO absolute $56000050;
GPG: TGPIO absolute $56000060;
GPH: TGPIO absolute $56000070;
GPJ: TGPIO absolute $560000D0;
MISCCR: longword absolute $56000080;
DCLKCON: longword absolute $56000084;
EXTINT0: longword absolute $56000088;
EXTINT1: longword absolute $5600008C;
EXTINT2: longword absolute $56000090;
EINTFLT0: longword absolute $56000094;
EINTFLT1: longword absolute $56000098;
EINTFLT2: longword absolute $5600009C;
EINTFLT3: longword absolute $560000A0;
EINTMASK: longword absolute $560000A4;
EINTPEND: longword absolute $560000A8;
GSTATUS0: longword absolute $560000AC;
GSTATUS1: longword absolute $560000B0;
GSTATUS2: longword absolute $560000B4;
GSTATUS3: longword absolute $560000B8;
GSTATUS4: longword absolute $560000BC;
MSLCON: longword absolute $560000CC;
{ RTC }
RTCCON: byte absolute $57000040;
TICNT: byte absolute $57000044;
RTCALM: byte absolute $57000050;
ALMSEC: byte absolute $57000054;
ALMMIN: byte absolute $57000058;
ALMHOUR: byte absolute $5700005C;
ALMDATE: byte absolute $57000060;
ALMMON: byte absolute $57000064;
ALMYEAR: byte absolute $57000068;
BCDSEC: byte absolute $57000070;
BCDMIN: byte absolute $57000074;
BCDHOUR: byte absolute $57000078;
BCDDATE: byte absolute $5700007C;
BCDDAY: byte absolute $57000080;
BCDMON: byte absolute $57000084;
BCDYEAR: byte absolute $57000088;
RTCLBAT: byte absolute $5700006C;
{ AD converter }
ADCCON: longword absolute $58000000;
ADCTSC: longword absolute $58000004;
ADCDLY: longword absolute $58000008;
ADCDAT0: longword absolute $5800000C;
ADCDAT1: longword absolute $58000010;
ADCUPDN: longword absolute $58000014;
type
TSPI = packed record
SPCON,
SPSTA,
SPPIN,
SPPRE,
SPTDAT,
SPRDAT: longword;
end;
var
{ SPI }
SPI0: TSPI absolute $59000000;
SPI1: TSPI absolute $59000020;
{ SD Interface }
SDICON: longword absolute $5A000000;
SDIPRE: longword absolute $5A000004;
SDICARG: longword absolute $5A000008;
SDICCON: longword absolute $5A00000C;
SDICSTA: longword absolute $5A000010;
SDIRSP0: longword absolute $5A000014;
SDIRSP1: longword absolute $5A000018;
SDIRSP2: longword absolute $5A00001C;
SDIRSP3: longword absolute $5A000020;
SDIDTIMER: longword absolute $5A000024;
SDIBSIZE: longword absolute $5A000028;
SDIDCON: longword absolute $5A00002C;
SDIDCNT: longword absolute $5A000030;
SDIDSTA: longword absolute $5A000034;
SDIFSTA: longword absolute $5A000038;
SDIIMSK: longword absolute $5A00003C;
SDIDAT: byte absolute $5A000040;
implementation
procedure AT91F_Default_FIQ_handler; assembler; nostackframe; public name 'AT91F_Default_FIQ_handler';
asm
.Lloop:
b .Lloop
end;
procedure AT91F_Default_IRQ_handler; assembler; nostackframe; public name 'AT91F_Default_IRQ_handler';
asm
.Lloop:
b .Lloop
end;
procedure AT91F_Spurious_handler; assembler; nostackframe; public name 'AT91F_Spurious_handler';
procedure UndefinedInstrHandler; external name 'UndefinedInstrHandler';
procedure SWIHandler; external name 'SWIHandler';
procedure PrefetchAbortHandler; external name 'PrefetchAbortHandler';
procedure DataAbortHandler; external name 'DataAbortHandler';
procedure IRQHandler; external name 'IRQHandler';
procedure FIQHandler; external name 'FIQHandler';
procedure DefaultExceptionHandler; assembler; nostackframe;
asm
.Lloop:
b .Lloop
@ -370,45 +357,40 @@ unit sc32442b;
.align 16
.globl _start
b _start
b .LUndefined_Addr // Undefined Instruction vector
b .LSWI_Addr // Software Interrupt vector
b .LPrefetch_Addr // Prefetch abort vector
b .LAbort_Addr // Data abort vector
ldr pc, .LUndefined_Addr // Undefined Instruction vector
ldr pc, .LSWI_Addr // Software Interrupt vector
ldr pc, .LPrefetch_Addr // Prefetch abort vector
ldr pc, .LAbort_Addr // Data abort vector
nop // reserved
b .LIRQ_Addr // Interrupt Request (IRQ) vector
b .LFIQ_Addr // Fast interrupt request (FIQ) vector
ldr pc, .LIRQ_Addr // Interrupt Request (IRQ) vector
ldr pc, .LFIQ_Addr // Fast interrupt request (FIQ) vector
.LUndefined_Addr:
ldr r0,.L1
ldr pc,[r0]
.long UndefinedInstrHandler
.LSWI_Addr:
ldr r0,.L2
ldr pc,[r0]
.long SWIHandler
.LPrefetch_Addr:
ldr r0,.L3
ldr pc,[r0]
.long PrefetchAbortHandler
.LAbort_Addr:
ldr r0,.L4
ldr pc,[r0]
.long DataAbortHandler
.LIRQ_Addr:
ldr r0,.L5
ldr pc,[r0]
.long IRQHandler
.LFIQ_Addr:
ldr r0,.L5
ldr pc,[r0]
.long FIQHandler
.L1:
.long Undefined_Handler
.L2:
.long SWI_Handler
.L3:
.long Prefetch_Handler
.L4:
.long Abort_Handler
.L5:
.long IRQ_Handler
.L6:
.long FIQ_Handler
.weak UndefinedInstrHandler
.weak SWIHandler
.weak PrefetchAbortHandler
.weak DataAbortHandler
.weak IRQHandler
.weak FIQHandler
.set UndefinedInstrHandler, DefaultExceptionHandler
.set SWIHandler, DefaultExceptionHandler
.set PrefetchAbortHandler, DefaultExceptionHandler
.set DataAbortHandler, DefaultExceptionHandler
.set IRQHandler, DefaultExceptionHandler
.set FIQHandler, DefaultExceptionHandler
_start:
(*
@ -454,21 +436,6 @@ unit sc32442b;
msr CPSR_c, #0x1f // switch to System Mode, interrupts enabled
mov sp, r0
// for now, all handlers are set to a default one
ldr r1,.LDefaultHandlerAddr
ldr r0,.L1
str r1,[r0]
ldr r0,.L2
str r1,[r0]
ldr r0,.L3
str r1,[r0]
ldr r0,.L4
str r1,[r0]
ldr r0,.L5
str r1,[r0]
ldr r0,.L6
str r1,[r0]
// copy initialized data from flash to ram
ldr r1,.L_etext
ldr r2,.L_data
@ -502,11 +469,6 @@ unit sc32442b;
.long _edata
.L_stack_top:
.long _stack_top
.LDefaultHandlerAddr:
.long .LDefaultHandler
// default irq handler just returns
.LDefaultHandler:
mov pc,r14
.text
end;

683
rtl/embedded/arm/stm32f103.pp
View File

@ -1,683 +0,0 @@
{
Register definitions and utility code for STM32F103
Preliminary startup code - TODO: interrupt handler variables
Created by Jeppe Johansen 2009 - jepjoh2@kom.aau.dk
}
unit stm32f103;
{$goto on}
{$define stm32f103}
interface
type
TBitvector32 = bitpacked array[0..31] of 0..1;
{$PACKRECORDS 2}
const
PeripheralBase = $40000000;
FSMCBase = $60000000;
APB1Base = PeripheralBase;
APB2Base = PeripheralBase+$10000;
AHBBase = PeripheralBase+$20000;
SCS_BASE = $E000E000;
{ FSMC }
FSMCBank1NOR1 = FSMCBase+$00000000;
FSMCBank1NOR2 = FSMCBase+$04000000;
FSMCBank1NOR3 = FSMCBase+$08000000;
FSMCBank1NOR4 = FSMCBase+$0C000000;
FSMCBank1PSRAM1 = FSMCBase+$00000000;
FSMCBank1PSRAM2 = FSMCBase+$04000000;
FSMCBank1PSRAM3 = FSMCBase+$08000000;
FSMCBank1PSRAM4 = FSMCBase+$0C000000;
FSMCBank2NAND1 = FSMCBase+$10000000;
FSMCBank3NAND2 = FSMCBase+$20000000;
FSMCBank4PCCARD = FSMCBase+$30000000;
type
TTimerRegisters = record
CR1, res1,
CR2, res2,
SMCR, res3,
DIER, res4,
SR, res5,
EGR, res,
CCMR1, res6,
CCMR2, res7,
CCER, res8,
CNT, res9,
PSC, res10,
ARR, res11,
RCR, res12,
CCR1, res13,
CCR2, res14,
CCR3, res15,
CCR4, res16,
BDTR, res17,
DCR, res18,
DMAR, res19: Word;
end;
TRTCRegisters = record
CRH, res1,
CRL, res2,
PRLH, res3,
PRLL, res4,
DIVH, res5,
DIVL, res6,
CNTH, res7,
CNTL, res8,
ALRH, res9,
ALRL, res10: Word;
end;
TIWDGRegisters = record
KR, res1,
PR, res2,
RLR, res3,
SR, res4: word;
end;
TWWDGRegisters = record
CR, res2,
CFR, res3,
SR, res4: word;
end;
TSPIRegisters = record
CR1, res1,
CR2, res2,
SR, res3,
DR, res4,
CRCPR, res5,
RXCRCR, res6,
TXCRCR, res7,
I2SCFGR, res8,
I2SPR, res9: Word;
end;
TUSARTRegisters = record
SR, res1,
DR, res2,
BRR, res3,
CR1, res4,
CR2, res5,
CR3, res6,
GTPR, res7: Word;
end;
TI2CRegisters = record
CR1, res1,
CR2, res2,
OAR1, res3,
OAR2, res4,
DR, res5,
SR1, res6,
SR2, res7,
CCR, res8: word;
TRISE: byte;
end;
TUSBRegisters = record
EPR: array[0..7] of DWord;
res: array[0..7] of dword;
CNTR, res1,
ISTR, res2,
FNR, res3: Word;
DADDR: byte; res4: word; res5: byte;
BTABLE: Word;
end;
TUSBMem = packed array[0..511] of byte;
TCANMailbox = record
IR,
DTR,
DLR,
DHR: DWord;
end;
TCANRegisters = record
MCR,
MSR,
TSR,
RF0R,
RF1R,
IER,
ESR,
BTR: DWord;
res5: array[$020..$17F] of byte;
TX: array[0..2] of TCANMailbox;
RX: array[0..2] of TCANMailbox;
res6: array[$1D0..$1FF] of byte;
FMR,
FM1R,
res9: DWord;
FS1R, res10: word;
res11: DWord;
FFA1R, res12: word;
res13: DWord;
FA1R, res14: word;
res15: array[$220..$23F] of byte;
FOR1,
FOR2: DWord;
FB: array[1..13] of array[1..2] of DWord;
end;
TBKPRegisters = record
DR: array[1..10] of record data, res: word; end;
RTCCR,
CR,
CSR,
res1,res2: DWord;
DR2: array[11..42] of record data, res: word; end;
end;
TPwrRegisters = record
CR, res: word;
CSR: Word;
end;
TDACRegisters = record
CR,
SWTRIGR: DWord;
DHR12R1, res2,
DHR12L1, res3,
DHR8R1, res4,
DHR12R2, res5,
DHR12L2, res6,
DHR8R2, res7: word;
DHR12RD,
DHR12LD: DWord;
DHR8RD, res8,
DOR1, res9,
DOR2, res10: Word;
end;
TAFIORegisters = record
EVCR,
MAPR: DWord;
EXTICR: array[0..3] of DWord;
end;
TEXTIRegisters = record
IMR,
EMR,
RTSR,
FTSR,
SWIER,
PR: DWord;
end;
TPortRegisters = record
CRL,
CRH,
IDR,
ODR,
BSRR,
BRR,
LCKR: DWord;
end;
TADCRegisters = record
SR,
CR1,
CR2,
SMPR1,
SMPR2: DWord;
JOFR1, res2,
JOFR2, res3,
JOFR3, res4,
JOFR4, res5,
HTR, res6,
LTR, res7: word;
SQR1,
SQR2,
SQR3,
JSQR: DWord;
JDR1, res8,
JDR2, res9,
JDR3, res10,
JDR4, res11: Word;
DR: DWord;
end;
TSDIORegisters = record
POWER,
CLKCR,
ARG: DWord;
CMD, res3,
RESPCMD, res4: Word;
RESP1,
RESP2,
RESP3,
RESP4,
DTIMER,
DLEN: DWord;
DCTRL, res5: word;
DCOUNT,
STA,
ICR,
MASK,
FIFOCNT,
FIFO: DWord;
end;
TDMAChannel = record
CCR, res1,
CNDTR, res2: word;
CPAR,
CMAR,
res: DWord;
end;
TDMARegisters = record
ISR,
IFCR: DWord;
Channel: array[0..7] of TDMAChannel;
end;
TRCCRegisters = record
CR,
CFGR,
CIR,
APB2RSTR,
APB1RSTR,
AHBENR,
APB2ENR,
APB1ENR,
BDCR,
CSR: DWord;
end;
TCRCRegisters = record
DR: DWord;
IDR: byte; res1: word; res2: byte;
CR: byte;
end;
TFSMCRegisters = record
nothingyet: byte;
end;
TFlashRegisters = record
ACR,
KEYR,
OPTKEYR,
SR,
CR,
AR,
res,
OBR,
WRPR: DWord;
end;
TNVICRegisters = packed record
ISER: array[0..7] of longword;
reserved0: array[0..23] of longword;
ICER: array[0..7] of longword;
reserved1: array[0..23] of longword;
ISPR: array[0..7] of longword;
reserved2: array[0..23] of longword;
ICPR: array[0..7] of longword;
reserved3: array[0..23] of longword;
IABR: array[0..7] of longword;
reserved4: array[0..55] of longword;
IP: array[0..239] of longword;
reserved5: array[0..643] of longword;
STIR: longword;
end;
TSCBRegisters = packed record
CPUID, {!< CPU ID Base Register }
ICSR, {!< Interrupt Control State Register }
VTOR, {!< Vector Table Offset Register }
AIRCR, {!< Application Interrupt / Reset Control Register }
SCR, {!< System Control Register }
CCR: longword; {!< Configuration Control Register }
SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
SHCSR, {!< System Handler Control and State Register }
CFSR, {!< Configurable Fault Status Register }
HFSR, {!< Hard Fault Status Register }
DFSR, {!< Debug Fault Status Register }
MMFAR, {!< Mem Manage Address Register }
BFAR, {!< Bus Fault Address Register }
AFSR: longword; {!< Auxiliary Fault Status Register }
PFR: array[0..1] of longword; {!< Processor Feature Register }
DFR, {!< Debug Feature Register }
ADR: longword; {!< Auxiliary Feature Register }
MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
ISAR: array[0..4] of longword; {!< ISA Feature Register }
end;
TSysTickRegisters = packed record
Ctrl,
Load,
Val,
Calib: longword;
end;
{$ALIGN 2}
var
{ Timers }
Timer1: TTimerRegisters absolute (APB2Base+$2C00);
Timer2: TTimerRegisters absolute (APB1Base+$0000);
Timer3: TTimerRegisters absolute (APB1Base+$0400);
Timer4: TTimerRegisters absolute (APB1Base+$0800);
Timer5: TTimerRegisters absolute (APB1Base+$0C00);
Timer6: TTimerRegisters absolute (APB1Base+$1000);
Timer7: TTimerRegisters absolute (APB1Base+$1400);
Timer8: TTimerRegisters absolute (APB2Base+$3400);
{ RTC }
RTC: TRTCRegisters absolute (APB1Base+$2800);
{ WDG }
WWDG: TWWDGRegisters absolute (APB1Base+$2C00);
IWDG: TIWDGRegisters absolute (APB1Base+$3000);
{ SPI }
SPI1: TSPIRegisters absolute (APB2Base+$3000);
SPI2: TSPIRegisters absolute (APB1Base+$3800);
SPI3: TSPIRegisters absolute (APB1Base+$3C00);
{ USART/UART }
USART1: TUSARTRegisters absolute (APB2Base+$3800);
USART2: TUSARTRegisters absolute (APB1Base+$4400);
USART3: TUSARTRegisters absolute (APB1Base+$4800);
UART4: TUSARTRegisters absolute (APB1Base+$4C00);
UART5: TUSARTRegisters absolute (APB1Base+$5000);
{ I2C }
I2C1: TI2CRegisters absolute (APB1Base+$5400);
I2C2: TI2CRegisters absolute (APB1Base+$5800);
{ USB }
USB: TUSBRegisters absolute (APB1Base+$5C00);
USBMem: TUSBMem absolute (APB1Base+$6000);
{ CAN }
CAN: TCANRegisters absolute (APB1Base+$6800);
{ BKP }
BKP: TBKPRegisters absolute (APB1Base+$6C00);
{ PWR }
PWR: TPwrRegisters absolute (APB1Base+$7000);
{ DAC }
DAC: TDACRegisters absolute (APB1Base+$7400);
{ GPIO }
AFIO: TAFIORegisters absolute (APB2Base+$0);
EXTI: TEXTIRegisters absolute (APB2Base+$0400);
PortA: TPortRegisters absolute (APB2Base+$0800);
PortB: TPortRegisters absolute (APB2Base+$0C00);
PortC: TPortRegisters absolute (APB2Base+$1000);
PortD: TPortRegisters absolute (APB2Base+$1400);
PortE: TPortRegisters absolute (APB2Base+$1800);
PortF: TPortRegisters absolute (APB2Base+$1C00);
PortG: TPortRegisters absolute (APB2Base+$2000);
{ ADC }
ADC1: TADCRegisters absolute (APB2Base+$2400);
ADC2: TADCRegisters absolute (APB2Base+$2800);
ADC3: TADCRegisters absolute (APB2Base+$3C00);
{ SDIO }
SDIO: TSDIORegisters absolute (APB2Base+$8000);
{ DMA }
DMA1: TDMARegisters absolute (AHBBase+$0000);
DMA2: TDMARegisters absolute (AHBBase+$0400);
{ RCC }
RCC: TRCCRegisters absolute (AHBBase+$1000);
{ Flash }
Flash: TFlashRegisters absolute (AHBBase+$2000);
{ CRC }
CRC: TCRCRegisters absolute (AHBBase+$3000);
{ SCB }
SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
{ SysTick }
SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
{ NVIC }
NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
var
NMI_Handler,
HardFault_Handler,
MemManage_Handler,
BusFault_Handler,
UsageFault_Handler,
SWI_Handler,
DebugMonitor_Handler,
PendingSV_Handler,
Systick_Handler: pointer;
implementation
var
_data: record end; external name '_data';
_edata: record end; external name '_edata';
_etext: record end; external name '_etext';
_bss_start: record end; external name '_bss_start';
_bss_end: record end; external name '_bss_end';
_stack_top: record end; external name '_stack_top';
procedure PASCALMAIN; external name 'PASCALMAIN';
procedure _FPC_haltproc; assembler; nostackframe; public name '_haltproc';
asm
.Lhalt:
b .Lhalt
end;
procedure _FPC_start; assembler; nostackframe;
label _start;
asm
.init
.balign 16
.long _stack_top // First entry in NVIC table is the new stack pointer
.long _start+1
//b _start // Reset
.long _start+1
//b .LNMI_Addr // Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector.
.long _start+1
//b .LHardFault_Addr // All class of fault
.long _start+1
//b .LMemManage_Addr // Memory management
.long _start+1
//b .LBusFault_Addr // Pre-fetch fault, memory access fault
.long _start+1
//b .LUsageFault_Addr // Undefined instruction or illegal state
.long _start+1
//nop // Reserved
.long _start+1
//nop // Reserved
.long _start+1
//nop // Reserved
.long _start+1
//nop // Reserved
.long _start+1
//b .LSWI_Addr // Software Interrupt vector
.long _start+1
//b .LDebugMonitor_Addr // Debug Monitor
.long _start+1
//nop // Reserved
.long _start+1
//b .LPendingSV_Addr // Pendable request for system service
.long _start+1
//b .LSystick_Addr // System tick timer
//17
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
//20
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.long .LDefaultHandler+1
.LNMI_Addr:
ldr r0,.L1
ldr pc,[r0]
.LHardFault_Addr:
ldr r0,.L2
ldr pc,[r0]
.LMemManage_Addr:
ldr r0,.L3
ldr pc,[r0]
.LBusFault_Addr:
ldr r0,.L4
ldr pc,[r0]
.LUsageFault_Addr:
ldr r0,.L5
ldr pc,[r0]
.LSWI_Addr:
ldr r0,.L6
ldr pc,[r0]
.LDebugMonitor_Addr:
ldr r0,.L7
ldr pc,[r0]
.LPendingSV_Addr:
ldr r0,.L8
ldr pc,[r0]
.LSystick_Addr:
ldr r0,.L9
ldr pc,[r0]
.L1:
.long NMI_Handler
.L2:
.long HardFault_Handler
.L3:
.long MemManage_Handler
.L4:
.long BusFault_Handler
.L5:
.long UsageFault_Handler
.L6:
.long SWI_Handler
.L7:
.long DebugMonitor_Handler
.L8:
.long PendingSV_Handler
.L9:
.long Systick_Handler
.globl _start
.text
_start:
// Copy initialized data to ram
ldr r1,.L_etext
ldr r2,.L_data
ldr r3,.L_edata
.Lcopyloop:
cmp r2,r3
ittt ls
ldrls r0,[r1],#4
strls r0,[r2],#4
bls .Lcopyloop
// clear onboard ram
ldr r1,.L_bss_start
ldr r2,.L_bss_end
mov r0,#0
.Lzeroloop:
cmp r1,r2
itt ls
strls r0,[r1],#4
bls .Lzeroloop
b PASCALMAIN
b _FPC_haltproc
.L_bss_start:
.long _bss_start
.L_bss_end:
.long _bss_end
.L_etext:
.long _etext
.L_data:
.long _data
.L_edata:
.long _edata
.LDefaultHandlerAddr:
.long .LDefaultHandler
// default irq handler just returns
.LDefaultHandler:
mov pc,r14
end;
end.

788
rtl/embedded/arm/stm32f10x_conn.pp Normal file
View File

@ -0,0 +1,788 @@
{
Register definitions and utility code for STM32F10x - Connectivity line
Created by Jeppe Johansen 2012 - jeppe@j-software.dk
}
unit stm32f10x_conn;
{$goto on}
{$define stm32f10x_conn}
interface
type
TBitvector32 = bitpacked array[0..31] of 0..1;
{$PACKRECORDS 2}
const
PeripheralBase = $40000000;
FSMCBase = $60000000;
APB1Base = PeripheralBase;
APB2Base = PeripheralBase+$10000;
AHBBase = PeripheralBase+$20000;
SCS_BASE = $E000E000;
{ FSMC }
FSMCBank1NOR1 = FSMCBase+$00000000;
FSMCBank1NOR2 = FSMCBase+$04000000;
FSMCBank1NOR3 = FSMCBase+$08000000;
FSMCBank1NOR4 = FSMCBase+$0C000000;
FSMCBank1PSRAM1 = FSMCBase+$00000000;
FSMCBank1PSRAM2 = FSMCBase+$04000000;
FSMCBank1PSRAM3 = FSMCBase+$08000000;
FSMCBank1PSRAM4 = FSMCBase+$0C000000;
FSMCBank2NAND1 = FSMCBase+$10000000;
FSMCBank3NAND2 = FSMCBase+$20000000;
FSMCBank4PCCARD = FSMCBase+$30000000;
type
TTimerRegisters = record
CR1, res1,
CR2, res2,
SMCR, res3,
DIER, res4,
SR, res5,
EGR, res,
CCMR1, res6,
CCMR2, res7,
CCER, res8,
CNT, res9,
PSC, res10,
ARR, res11,
RCR, res12,
CCR1, res13,
CCR2, res14,
CCR3, res15,
CCR4, res16,
BDTR, res17,
DCR, res18,
DMAR, res19: Word;
end;
TRTCRegisters = record
CRH, res1,
CRL, res2,
PRLH, res3,
PRLL, res4,
DIVH, res5,
DIVL, res6,
CNTH, res7,
CNTL, res8,
ALRH, res9,
ALRL, res10: Word;
end;
TIWDGRegisters = record
KR, res1,
PR, res2,
RLR, res3,
SR, res4: word;
end;
TWWDGRegisters = record
CR, res2,
CFR, res3,
SR, res4: word;
end;
TSPIRegisters = record
CR1, res1,
CR2, res2,
SR, res3,
DR, res4,
CRCPR, res5,
RXCRCR, res6,
TXCRCR, res7,
I2SCFGR, res8,
I2SPR, res9: Word;
end;
TUSARTRegisters = record
SR, res1,
DR, res2,
BRR, res3,
CR1, res4,
CR2, res5,
CR3, res6,
GTPR, res7: Word;
end;
TI2CRegisters = record
CR1, res1,
CR2, res2,
OAR1, res3,
OAR2, res4,
DR, res5,
SR1, res6,
SR2, res7,
CCR, res8: word;
TRISE: byte;
end;
TUSBRegisters = record
EPR: array[0..7] of longword;
res: array[0..7] of longword;
CNTR, res1,
ISTR, res2,
FNR, res3: Word;
DADDR: byte; res4: word; res5: byte;
BTABLE: Word;
end;
TUSBMem = packed array[0..511] of byte;
TCANMailbox = record
IR,
DTR,
DLR,
DHR: longword;
end;
TCANRegisters = record
MCR,
MSR,
TSR,
RF0R,
RF1R,
IER,
ESR,
BTR: longword;
res5: array[$020..$17F] of byte;
TX: array[0..2] of TCANMailbox;
RX: array[0..2] of TCANMailbox;
res6: array[$1D0..$1FF] of byte;
FMR,
FM1R,
res9: longword;
FS1R, res10: word;
res11: longword;
FFA1R, res12: word;
res13: longword;
FA1R, res14: word;
res15: array[$220..$23F] of byte;
FOR1,
FOR2: longword;
FB: array[1..13] of array[1..2] of longword;
end;
TBKPRegisters = record
DR: array[1..10] of record data, res: word; end;
RTCCR,
CR,
CSR,
res1,res2: longword;
DR2: array[11..42] of record data, res: word; end;
end;
TPwrRegisters = record
CR, res: word;
CSR: Word;
end;
TDACRegisters = record
CR,
SWTRIGR: longword;
DHR12R1, res2,
DHR12L1, res3,
DHR8R1, res4,
DHR12R2, res5,
DHR12L2, res6,
DHR8R2, res7: word;
DHR12RD,
DHR12LD: longword;
DHR8RD, res8,
DOR1, res9,
DOR2, res10: Word;
end;
TAFIORegisters = record
EVCR,
MAPR: longword;
EXTICR: array[0..3] of longword;
end;
TEXTIRegisters = record
IMR,
EMR,
RTSR,
FTSR,
SWIER,
PR: longword;
end;
TPortRegisters = record
CRL,
CRH,
IDR,
ODR,
BSRR,
BRR,
LCKR: longword;
end;
TADCRegisters = record
SR,
CR1,
CR2,
SMPR1,
SMPR2: longword;
JOFR1, res2,
JOFR2, res3,
JOFR3, res4,
JOFR4, res5,
HTR, res6,
LTR, res7: word;
SQR1,
SQR2,
SQR3,
JSQR: longword;
JDR1, res8,
JDR2, res9,
JDR3, res10,
JDR4, res11: Word;
DR: longword;
end;
TSDIORegisters = record
POWER,
CLKCR,
ARG: longword;
CMD, res3,
RESPCMD, res4: Word;
RESP1,
RESP2,
RESP3,
RESP4,
DTIMER,
DLEN: longword;
DCTRL, res5: word;
DCOUNT,
STA,
ICR,
MASK,
FIFOCNT,
FIFO: longword;
end;
TDMAChannel = record
CCR, res1,
CNDTR, res2: word;
CPAR,
CMAR,
res: longword;
end;
TDMARegisters = record
ISR,
IFCR: longword;
Channel: array[0..7] of TDMAChannel;
end;
TRCCRegisters = record
CR,
CFGR,
CIR,
APB2RSTR,
APB1RSTR,
AHBENR,
APB2ENR,
APB1ENR,
BDCR,
CSR: longword;
end;
TCRCRegisters = record
DR: longword;
IDR: byte; res1: word; res2: byte;
CR: byte;
end;
TFSMCRegisters = record
nothingyet: byte;
end;
TFlashRegisters = record
ACR,
KEYR,
OPTKEYR,
SR,
CR,
AR,
res,
OBR,
WRPR: longword;
end;
TNVICRegisters = record
ISER: array[0..7] of longword;
reserved0: array[0..23] of longword;
ICER: array[0..7] of longword;
reserved1: array[0..23] of longword;
ISPR: array[0..7] of longword;
reserved2: array[0..23] of longword;
ICPR: array[0..7] of longword;
reserved3: array[0..23] of longword;
IABR: array[0..7] of longword;
reserved4: array[0..55] of longword;
IP: array[0..239] of longword;
reserved5: array[0..643] of longword;
STIR: longword;
end;
TSCBRegisters = record
CPUID, {!< CPU ID Base Register }
ICSR, {!< Interrupt Control State Register }
VTOR, {!< Vector Table Offset Register }
AIRCR, {!< Application Interrupt / Reset Control Register }
SCR, {!< System Control Register }
CCR: longword; {!< Configuration Control Register }
SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
SHCSR, {!< System Handler Control and State Register }
CFSR, {!< Configurable Fault Status Register }
HFSR, {!< Hard Fault Status Register }
DFSR, {!< Debug Fault Status Register }
MMFAR, {!< Mem Manage Address Register }
BFAR, {!< Bus Fault Address Register }
AFSR: longword; {!< Auxiliary Fault Status Register }
PFR: array[0..1] of longword; {!< Processor Feature Register }
DFR, {!< Debug Feature Register }
ADR: longword; {!< Auxiliary Feature Register }
MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
ISAR: array[0..4] of longword; {!< ISA Feature Register }
end;
TSysTickRegisters = record
Ctrl,
Load,
Val,
Calib: longword;
end;
{$ALIGN 2}
var
{ Timers }
Timer1: TTimerRegisters absolute (APB2Base+$2C00);
Timer2: TTimerRegisters absolute (APB1Base+$0000);
Timer3: TTimerRegisters absolute (APB1Base+$0400);
Timer4: TTimerRegisters absolute (APB1Base+$0800);
Timer5: TTimerRegisters absolute (APB1Base+$0C00);
Timer6: TTimerRegisters absolute (APB1Base+$1000);
Timer7: TTimerRegisters absolute (APB1Base+$1400);
Timer8: TTimerRegisters absolute (APB2Base+$3400);
{ RTC }
RTC: TRTCRegisters absolute (APB1Base+$2800);
{ WDG }
WWDG: TWWDGRegisters absolute (APB1Base+$2C00);
IWDG: TIWDGRegisters absolute (APB1Base+$3000);
{ SPI }
SPI1: TSPIRegisters absolute (APB2Base+$3000);
SPI2: TSPIRegisters absolute (APB1Base+$3800);
SPI3: TSPIRegisters absolute (APB1Base+$3C00);
{ USART/UART }
USART1: TUSARTRegisters absolute (APB2Base+$3800);
USART2: TUSARTRegisters absolute (APB1Base+$4400);
USART3: TUSARTRegisters absolute (APB1Base+$4800);
UART4: TUSARTRegisters absolute (APB1Base+$4C00);
UART5: TUSARTRegisters absolute (APB1Base+$5000);
{ I2C }
I2C1: TI2CRegisters absolute (APB1Base+$5400);
I2C2: TI2CRegisters absolute (APB1Base+$5800);
{ USB }
USB: TUSBRegisters absolute (APB1Base+$5C00);
USBMem: TUSBMem absolute (APB1Base+$6000);
{ CAN }
CAN: TCANRegisters absolute (APB1Base+$6800);
{ BKP }
BKP: TBKPRegisters absolute (APB1Base+$6C00);
{ PWR }
PWR: TPwrRegisters absolute (APB1Base+$7000);
{ DAC }
DAC: TDACRegisters absolute (APB1Base+$7400);
{ GPIO }
AFIO: TAFIORegisters absolute (APB2Base+$0);
EXTI: TEXTIRegisters absolute (APB2Base+$0400);
PortA: TPortRegisters absolute (APB2Base+$0800);
PortB: TPortRegisters absolute (APB2Base+$0C00);
PortC: TPortRegisters absolute (APB2Base+$1000);
PortD: TPortRegisters absolute (APB2Base+$1400);
PortE: TPortRegisters absolute (APB2Base+$1800);
PortF: TPortRegisters absolute (APB2Base+$1C00);
PortG: TPortRegisters absolute (APB2Base+$2000);
{ ADC }
ADC1: TADCRegisters absolute (APB2Base+$2400);
ADC2: TADCRegisters absolute (APB2Base+$2800);
ADC3: TADCRegisters absolute (APB2Base+$3C00);
{ SDIO }
SDIO: TSDIORegisters absolute (APB2Base+$8000);
{ DMA }
DMA1: TDMARegisters absolute (AHBBase+$0000);
DMA2: TDMARegisters absolute (AHBBase+$0400);
{ RCC }
RCC: TRCCRegisters absolute (AHBBase+$1000);
{ Flash }
Flash: TFlashRegisters absolute (AHBBase+$2000);
{ CRC }
CRC: TCRCRegisters absolute (AHBBase+$3000);
{ SCB }
SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
{ SysTick }
SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
{ NVIC }
NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
implementation
procedure NMI_interrupt; external name 'NMI_interrupt';
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
procedure MemManage_interrupt; external name 'MemManage_interrupt';
procedure BusFault_interrupt; external name 'BusFault_interrupt';
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
procedure SWI_interrupt; external name 'SWI_interrupt';
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
procedure SysTick_interrupt; external name 'SysTick_interrupt';
procedure Window_Watchdog_interrupt; external name 'Window_Watchdog_interrupt';
procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
procedure Tamper_interrupt; external name 'Tamper_interrupt';
procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
procedure CAN1_TX_interrupts; external name 'CAN1_TX_interrupts';
procedure CAN1_RX0_interrupts; external name 'CAN1_RX0_interrupts';
procedure CAN1_RX1_interrupt; external name 'CAN1_RX1_interrupt';
procedure CAN1_SCE_interrupt; external name 'CAN1_SCE_interrupt';
procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
procedure TIM1_Break_interrupt; external name 'TIM1_Break_interrupt';
procedure TIM1_Update_interrupt; external name 'TIM1_Update_interrupt';
procedure TIM1_Trigger_and_Commutation_interrupts; external name 'TIM1_Trigger_and_Commutation_interrupts';
procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
procedure USB_OTG_FS_Wakeup_through_EXTI_line_interrupt; external name 'USB_OTG_FS_Wakeup_through_EXTI_line_interrupt';
procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
procedure DMA2_Channel4_global_interrupt; external name 'DMA2_Channel4_global_interrupt';
procedure DMA2_Channel5_global_interrupt; external name 'DMA2_Channel5_global_interrupt';
procedure Ethernet_global_interrupt; external name 'Ethernet_global_interrupt';
procedure Ethernet_Wakeup_through_EXTI_line_interrupt; external name 'Ethernet_Wakeup_through_EXTI_line_interrupt';
procedure CAN2_TX_interrupts; external name 'CAN2_TX_interrupts';
procedure CAN2_RX0_interrupts; external name 'CAN2_RX0_interrupts';
procedure CAN2_RX1_interrupt; external name 'CAN2_RX1_interrupt';
procedure CAN2_SCE_interrupt; external name 'CAN2_SCE_interrupt';
procedure USB_On_The_Go_FS_global_interrupt; external name 'USB_On_The_Go_FS_global_interrupt';
{$i cortexm3_start.inc}
procedure Vectors; assembler; nostackframe;
label interrupt_vectors;
asm
.section ".init.interrupt_vectors"
interrupt_vectors:
.long _stack_top
.long Startup
.long NMI_interrupt
.long Hardfault_interrupt
.long MemManage_interrupt
.long BusFault_interrupt
.long UsageFault_interrupt
.long 0
.long 0
.long 0
.long 0
.long SWI_interrupt
.long DebugMonitor_interrupt
.long 0
.long PendingSV_interrupt
.long SysTick_interrupt
.long Window_Watchdog_interrupt
.long PVD_through_EXTI_Line_detection_interrupt
.long Tamper_interrupt
.long RTC_global_interrupt
.long Flash_global_interrupt
.long RCC_global_interrupt
.long EXTI_Line0_interrupt
.long EXTI_Line1_interrupt
.long EXTI_Line2_interrupt
.long EXTI_Line3_interrupt
.long EXTI_Line4_interrupt
.long DMA1_Channel1_global_interrupt
.long DMA1_Channel2_global_interrupt
.long DMA1_Channel3_global_interrupt
.long DMA1_Channel4_global_interrupt
.long DMA1_Channel5_global_interrupt
.long DMA1_Channel6_global_interrupt
.long DMA1_Channel7_global_interrupt
.long ADC1_and_ADC2_global_interrupt
.long CAN1_TX_interrupts
.long CAN1_RX0_interrupts
.long CAN1_RX1_interrupt
.long CAN1_SCE_interrupt
.long EXTI_Line9_5_interrupts
.long TIM1_Break_interrupt
.long TIM1_Update_interrupt
.long TIM1_Trigger_and_Commutation_interrupts
.long TIM1_Capture_Compare_interrupt
.long TIM2_global_interrupt
.long TIM3_global_interrupt
.long TIM4_global_interrupt
.long I2C1_event_interrupt
.long I2C1_error_interrupt
.long I2C2_event_interrupt
.long I2C2_error_interrupt
.long SPI1_global_interrupt
.long SPI2_global_interrupt
.long USART1_global_interrupt
.long USART2_global_interrupt
.long USART3_global_interrupt
.long EXTI_Line15_10_interrupts
.long RTC_alarm_through_EXTI_line_interrupt
.long USB_OTG_FS_Wakeup_through_EXTI_line_interrupt
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long TIM5_global_interrupt
.long SPI3_global_interrupt
.long UART4_global_interrupt
.long UART5_global_interrupt
.long TIM6_global_interrupt
.long TIM7_global_interrupt
.long DMA2_Channel1_global_interrupt
.long DMA2_Channel2_global_interrupt
.long DMA2_Channel3_global_interrupt
.long DMA2_Channel4_global_interrupt
.long DMA2_Channel5_global_interrupt
.long Ethernet_global_interrupt
.long Ethernet_Wakeup_through_EXTI_line_interrupt
.long CAN2_TX_interrupts
.long CAN2_RX0_interrupts
.long CAN2_RX1_interrupt
.long CAN2_SCE_interrupt
.long USB_On_The_Go_FS_global_interrupt
.weak NMI_interrupt
.weak Hardfault_interrupt
.weak MemManage_interrupt
.weak BusFault_interrupt
.weak UsageFault_interrupt
.weak SWI_interrupt
.weak DebugMonitor_interrupt
.weak PendingSV_interrupt
.weak SysTick_interrupt
.weak Window_Watchdog_interrupt
.weak PVD_through_EXTI_Line_detection_interrupt
.weak Tamper_interrupt
.weak RTC_global_interrupt
.weak Flash_global_interrupt
.weak RCC_global_interrupt
.weak EXTI_Line0_interrupt
.weak EXTI_Line1_interrupt
.weak EXTI_Line2_interrupt
.weak EXTI_Line3_interrupt
.weak EXTI_Line4_interrupt
.weak DMA1_Channel1_global_interrupt
.weak DMA1_Channel2_global_interrupt
.weak DMA1_Channel3_global_interrupt
.weak DMA1_Channel4_global_interrupt
.weak DMA1_Channel5_global_interrupt
.weak DMA1_Channel6_global_interrupt
.weak DMA1_Channel7_global_interrupt
.weak ADC1_and_ADC2_global_interrupt
.weak CAN1_TX_interrupts
.weak CAN1_RX0_interrupts
.weak CAN1_RX1_interrupt
.weak CAN1_SCE_interrupt
.weak EXTI_Line9_5_interrupts
.weak TIM1_Break_interrupt
.weak TIM1_Update_interrupt
.weak TIM1_Trigger_and_Commutation_interrupts
.weak TIM1_Capture_Compare_interrupt
.weak TIM2_global_interrupt
.weak TIM3_global_interrupt
.weak TIM4_global_interrupt
.weak I2C1_event_interrupt
.weak I2C1_error_interrupt
.weak I2C2_event_interrupt
.weak I2C2_error_interrupt
.weak SPI1_global_interrupt
.weak SPI2_global_interrupt
.weak USART1_global_interrupt
.weak USART2_global_interrupt
.weak USART3_global_interrupt
.weak EXTI_Line15_10_interrupts
.weak RTC_alarm_through_EXTI_line_interrupt
.weak USB_OTG_FS_Wakeup_through_EXTI_line_interrupt
.weak TIM5_global_interrupt
.weak SPI3_global_interrupt
.weak UART4_global_interrupt
.weak UART5_global_interrupt
.weak TIM6_global_interrupt
.weak TIM7_global_interrupt
.weak DMA2_Channel1_global_interrupt
.weak DMA2_Channel2_global_interrupt
.weak DMA2_Channel3_global_interrupt
.weak DMA2_Channel4_global_interrupt
.weak DMA2_Channel5_global_interrupt
.weak Ethernet_global_interrupt
.weak Ethernet_Wakeup_through_EXTI_line_interrupt
.weak CAN2_TX_interrupts
.weak CAN2_RX0_interrupts
.weak CAN2_RX1_interrupt
.weak CAN2_SCE_interrupt
.weak USB_On_The_Go_FS_global_interrupt
.set NMI_interrupt, Startup
.set Hardfault_interrupt, Startup
.set MemManage_interrupt, Startup
.set BusFault_interrupt, Startup
.set UsageFault_interrupt, Startup
.set SWI_interrupt, Startup
.set DebugMonitor_interrupt, Startup
.set PendingSV_interrupt, Startup
.set SysTick_interrupt, Startup
.set Window_Watchdog_interrupt, Startup
.set PVD_through_EXTI_Line_detection_interrupt, Startup
.set Tamper_interrupt, Startup
.set RTC_global_interrupt, Startup
.set Flash_global_interrupt, Startup
.set RCC_global_interrupt, Startup
.set EXTI_Line0_interrupt, Startup
.set EXTI_Line1_interrupt, Startup
.set EXTI_Line2_interrupt, Startup
.set EXTI_Line3_interrupt, Startup
.set EXTI_Line4_interrupt, Startup
.set DMA1_Channel1_global_interrupt, Startup
.set DMA1_Channel2_global_interrupt, Startup
.set DMA1_Channel3_global_interrupt, Startup
.set DMA1_Channel4_global_interrupt, Startup
.set DMA1_Channel5_global_interrupt, Startup
.set DMA1_Channel6_global_interrupt, Startup
.set DMA1_Channel7_global_interrupt, Startup
.set ADC1_and_ADC2_global_interrupt, Startup
.set CAN1_TX_interrupts, Startup
.set CAN1_RX0_interrupts, Startup
.set CAN1_RX1_interrupt, Startup
.set CAN1_SCE_interrupt, Startup
.set EXTI_Line9_5_interrupts, Startup
.set TIM1_Break_interrupt, Startup
.set TIM1_Update_interrupt, Startup
.set TIM1_Trigger_and_Commutation_interrupts, Startup
.set TIM1_Capture_Compare_interrupt, Startup
.set TIM2_global_interrupt, Startup
.set TIM3_global_interrupt, Startup
.set TIM4_global_interrupt, Startup
.set I2C1_event_interrupt, Startup
.set I2C1_error_interrupt, Startup
.set I2C2_event_interrupt, Startup
.set I2C2_error_interrupt, Startup
.set SPI1_global_interrupt, Startup
.set SPI2_global_interrupt, Startup
.set USART1_global_interrupt, Startup
.set USART2_global_interrupt, Startup
.set USART3_global_interrupt, Startup
.set EXTI_Line15_10_interrupts, Startup
.set RTC_alarm_through_EXTI_line_interrupt, Startup
.set USB_OTG_FS_Wakeup_through_EXTI_line_interrupt, Startup
.set TIM5_global_interrupt, Startup
.set SPI3_global_interrupt, Startup
.set UART4_global_interrupt, Startup
.set UART5_global_interrupt, Startup
.set TIM6_global_interrupt, Startup
.set TIM7_global_interrupt, Startup
.set DMA2_Channel1_global_interrupt, Startup
.set DMA2_Channel2_global_interrupt, Startup
.set DMA2_Channel3_global_interrupt, Startup
.set DMA2_Channel4_global_interrupt, Startup
.set DMA2_Channel5_global_interrupt, Startup
.set Ethernet_global_interrupt, Startup
.set Ethernet_Wakeup_through_EXTI_line_interrupt, Startup
.set CAN2_TX_interrupts, Startup
.set CAN2_RX0_interrupts, Startup
.set CAN2_RX1_interrupt, Startup
.set CAN2_SCE_interrupt, Startup
.set USB_On_The_Go_FS_global_interrupt, Startup
.text
end;
end.

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rtl/embedded/arm/stm32f10x_hd.pp Normal file
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{
Register definitions and utility code for STM32F10x - HD density
Created by Jeppe Johansen 2012 - jeppe@j-software.dk
}
unit stm32f10x_hd;
{$goto on}
{$define stm32f10x_hd}
interface
type
TBitvector32 = bitpacked array[0..31] of 0..1;
{$PACKRECORDS 2}
const
PeripheralBase = $40000000;
FSMCBase = $60000000;
APB1Base = PeripheralBase;
APB2Base = PeripheralBase+$10000;
AHBBase = PeripheralBase+$20000;
SCS_BASE = $E000E000;
{ FSMC }
FSMCBank1NOR1 = FSMCBase+$00000000;
FSMCBank1NOR2 = FSMCBase+$04000000;
FSMCBank1NOR3 = FSMCBase+$08000000;
FSMCBank1NOR4 = FSMCBase+$0C000000;
FSMCBank1PSRAM1 = FSMCBase+$00000000;
FSMCBank1PSRAM2 = FSMCBase+$04000000;
FSMCBank1PSRAM3 = FSMCBase+$08000000;
FSMCBank1PSRAM4 = FSMCBase+$0C000000;
FSMCBank2NAND1 = FSMCBase+$10000000;
FSMCBank3NAND2 = FSMCBase+$20000000;
FSMCBank4PCCARD = FSMCBase+$30000000;
type
TTimerRegisters = record
CR1, res1,
CR2, res2,
SMCR, res3,
DIER, res4,
SR, res5,
EGR, res,
CCMR1, res6,
CCMR2, res7,
CCER, res8,
CNT, res9,
PSC, res10,
ARR, res11,
RCR, res12,
CCR1, res13,
CCR2, res14,
CCR3, res15,
CCR4, res16,
BDTR, res17,
DCR, res18,
DMAR, res19: Word;
end;
TRTCRegisters = record
CRH, res1,
CRL, res2,
PRLH, res3,
PRLL, res4,
DIVH, res5,
DIVL, res6,
CNTH, res7,
CNTL, res8,
ALRH, res9,
ALRL, res10: Word;
end;
TIWDGRegisters = record
KR, res1,
PR, res2,
RLR, res3,
SR, res4: word;
end;
TWWDGRegisters = record
CR, res2,
CFR, res3,
SR, res4: word;
end;
TSPIRegisters = record
CR1, res1,
CR2, res2,
SR, res3,
DR, res4,
CRCPR, res5,
RXCRCR, res6,
TXCRCR, res7,
I2SCFGR, res8,
I2SPR, res9: Word;
end;
TUSARTRegisters = record
SR, res1,
DR, res2,
BRR, res3,
CR1, res4,
CR2, res5,
CR3, res6,
GTPR, res7: Word;
end;
TI2CRegisters = record
CR1, res1,
CR2, res2,
OAR1, res3,
OAR2, res4,
DR, res5,
SR1, res6,
SR2, res7,
CCR, res8: word;
TRISE: byte;
end;
TUSBRegisters = record
EPR: array[0..7] of longword;
res: array[0..7] of longword;
CNTR, res1,
ISTR, res2,
FNR, res3: Word;
DADDR: byte; res4: word; res5: byte;
BTABLE: Word;
end;
TUSBMem = packed array[0..511] of byte;
TCANMailbox = record
IR,
DTR,
DLR,
DHR: longword;
end;
TCANRegisters = record
MCR,
MSR,
TSR,
RF0R,
RF1R,
IER,
ESR,
BTR: longword;
res5: array[$020..$17F] of byte;
TX: array[0..2] of TCANMailbox;
RX: array[0..2] of TCANMailbox;
res6: array[$1D0..$1FF] of byte;
FMR,
FM1R,
res9: longword;
FS1R, res10: word;
res11: longword;
FFA1R, res12: word;
res13: longword;
FA1R, res14: word;
res15: array[$220..$23F] of byte;
FOR1,
FOR2: longword;
FB: array[1..13] of array[1..2] of longword;
end;
TBKPRegisters = record
DR: array[1..10] of record data, res: word; end;
RTCCR,
CR,
CSR,
res1,res2: longword;
DR2: array[11..42] of record data, res: word; end;
end;
TPwrRegisters = record
CR, res: word;
CSR: Word;
end;
TDACRegisters = record
CR,
SWTRIGR: longword;
DHR12R1, res2,
DHR12L1, res3,
DHR8R1, res4,
DHR12R2, res5,
DHR12L2, res6,
DHR8R2, res7: word;
DHR12RD,
DHR12LD: longword;
DHR8RD, res8,
DOR1, res9,
DOR2, res10: Word;
end;
TAFIORegisters = record
EVCR,
MAPR: longword;
EXTICR: array[0..3] of longword;
end;
TEXTIRegisters = record
IMR,
EMR,
RTSR,
FTSR,
SWIER,
PR: longword;
end;
TPortRegisters = record
CRL,
CRH,
IDR,
ODR,
BSRR,
BRR,
LCKR: longword;
end;
TADCRegisters = record
SR,
CR1,
CR2,
SMPR1,
SMPR2: longword;
JOFR1, res2,
JOFR2, res3,
JOFR3, res4,
JOFR4, res5,
HTR, res6,
LTR, res7: word;
SQR1,
SQR2,
SQR3,
JSQR: longword;
JDR1, res8,
JDR2, res9,
JDR3, res10,
JDR4, res11: Word;
DR: longword;
end;
TSDIORegisters = record
POWER,
CLKCR,
ARG: longword;
CMD, res3,
RESPCMD, res4: Word;
RESP1,
RESP2,
RESP3,
RESP4,
DTIMER,
DLEN: longword;
DCTRL, res5: word;
DCOUNT,
STA,
ICR,
MASK,
FIFOCNT,
FIFO: longword;
end;
TDMAChannel = record
CCR, res1,
CNDTR, res2: word;
CPAR,
CMAR,
res: longword;
end;
TDMARegisters = record
ISR,
IFCR: longword;
Channel: array[0..7] of TDMAChannel;
end;
TRCCRegisters = record
CR,
CFGR,
CIR,
APB2RSTR,
APB1RSTR,
AHBENR,
APB2ENR,
APB1ENR,
BDCR,
CSR: longword;
end;
TCRCRegisters = record
DR: longword;
IDR: byte; res1: word; res2: byte;
CR: byte;
end;
TFSMCRegisters = record
nothingyet: byte;
end;
TFlashRegisters = record
ACR,
KEYR,
OPTKEYR,
SR,
CR,
AR,
res,
OBR,
WRPR: longword;
end;
TNVICRegisters = record
ISER: array[0..7] of longword;
reserved0: array[0..23] of longword;
ICER: array[0..7] of longword;
reserved1: array[0..23] of longword;
ISPR: array[0..7] of longword;
reserved2: array[0..23] of longword;
ICPR: array[0..7] of longword;
reserved3: array[0..23] of longword;
IABR: array[0..7] of longword;
reserved4: array[0..55] of longword;
IP: array[0..239] of longword;
reserved5: array[0..643] of longword;
STIR: longword;
end;
TSCBRegisters = record
CPUID, {!< CPU ID Base Register }
ICSR, {!< Interrupt Control State Register }
VTOR, {!< Vector Table Offset Register }
AIRCR, {!< Application Interrupt / Reset Control Register }
SCR, {!< System Control Register }
CCR: longword; {!< Configuration Control Register }
SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
SHCSR, {!< System Handler Control and State Register }
CFSR, {!< Configurable Fault Status Register }
HFSR, {!< Hard Fault Status Register }
DFSR, {!< Debug Fault Status Register }
MMFAR, {!< Mem Manage Address Register }
BFAR, {!< Bus Fault Address Register }
AFSR: longword; {!< Auxiliary Fault Status Register }
PFR: array[0..1] of longword; {!< Processor Feature Register }
DFR, {!< Debug Feature Register }
ADR: longword; {!< Auxiliary Feature Register }
MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
ISAR: array[0..4] of longword; {!< ISA Feature Register }
end;
TSysTickRegisters = record
Ctrl,
Load,
Val,
Calib: longword;
end;
{$ALIGN 2}
var
{ Timers }
Timer1: TTimerRegisters absolute (APB2Base+$2C00);
Timer2: TTimerRegisters absolute (APB1Base+$0000);
Timer3: TTimerRegisters absolute (APB1Base+$0400);
Timer4: TTimerRegisters absolute (APB1Base+$0800);
Timer5: TTimerRegisters absolute (APB1Base+$0C00);
Timer6: TTimerRegisters absolute (APB1Base+$1000);
Timer7: TTimerRegisters absolute (APB1Base+$1400);
Timer8: TTimerRegisters absolute (APB2Base+$3400);
{ RTC }
RTC: TRTCRegisters absolute (APB1Base+$2800);
{ WDG }
WWDG: TWWDGRegisters absolute (APB1Base+$2C00);
IWDG: TIWDGRegisters absolute (APB1Base+$3000);
{ SPI }
SPI1: TSPIRegisters absolute (APB2Base+$3000);
SPI2: TSPIRegisters absolute (APB1Base+$3800);
SPI3: TSPIRegisters absolute (APB1Base+$3C00);
{ USART/UART }
USART1: TUSARTRegisters absolute (APB2Base+$3800);
USART2: TUSARTRegisters absolute (APB1Base+$4400);
USART3: TUSARTRegisters absolute (APB1Base+$4800);
UART4: TUSARTRegisters absolute (APB1Base+$4C00);
UART5: TUSARTRegisters absolute (APB1Base+$5000);
{ I2C }
I2C1: TI2CRegisters absolute (APB1Base+$5400);
I2C2: TI2CRegisters absolute (APB1Base+$5800);
{ USB }
USB: TUSBRegisters absolute (APB1Base+$5C00);
USBMem: TUSBMem absolute (APB1Base+$6000);
{ CAN }
CAN: TCANRegisters absolute (APB1Base+$6800);
{ BKP }
BKP: TBKPRegisters absolute (APB1Base+$6C00);
{ PWR }
PWR: TPwrRegisters absolute (APB1Base+$7000);
{ DAC }
DAC: TDACRegisters absolute (APB1Base+$7400);
{ GPIO }
AFIO: TAFIORegisters absolute (APB2Base+$0);
EXTI: TEXTIRegisters absolute (APB2Base+$0400);
PortA: TPortRegisters absolute (APB2Base+$0800);
PortB: TPortRegisters absolute (APB2Base+$0C00);
PortC: TPortRegisters absolute (APB2Base+$1000);
PortD: TPortRegisters absolute (APB2Base+$1400);
PortE: TPortRegisters absolute (APB2Base+$1800);
PortF: TPortRegisters absolute (APB2Base+$1C00);
PortG: TPortRegisters absolute (APB2Base+$2000);
{ ADC }
ADC1: TADCRegisters absolute (APB2Base+$2400);
ADC2: TADCRegisters absolute (APB2Base+$2800);
ADC3: TADCRegisters absolute (APB2Base+$3C00);
{ SDIO }
SDIO: TSDIORegisters absolute (APB2Base+$8000);
{ DMA }
DMA1: TDMARegisters absolute (AHBBase+$0000);
DMA2: TDMARegisters absolute (AHBBase+$0400);
{ RCC }
RCC: TRCCRegisters absolute (AHBBase+$1000);
{ Flash }
Flash: TFlashRegisters absolute (AHBBase+$2000);
{ CRC }
CRC: TCRCRegisters absolute (AHBBase+$3000);
{ SCB }
SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
{ SysTick }
SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
{ NVIC }
NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
implementation
procedure NMI_interrupt; external name 'NMI_interrupt';
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
procedure MemManage_interrupt; external name 'MemManage_interrupt';
procedure BusFault_interrupt; external name 'BusFault_interrupt';
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
procedure SWI_interrupt; external name 'SWI_interrupt';
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
procedure SysTick_interrupt; external name 'SysTick_interrupt';
procedure Window_watchdog_interrupt; external name 'Window_watchdog_interrupt';
procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
procedure Tamper_interrupt; external name 'Tamper_interrupt';
procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
procedure USB_High_Priority_or_CAN_TX_interrupts; external name 'USB_High_Priority_or_CAN_TX_interrupts';
procedure USB_Low_Priority_or_CAN_RX0_interrupts; external name 'USB_Low_Priority_or_CAN_RX0_interrupts';
procedure CAN_RX1_interrupt; external name 'CAN_RX1_interrupt';
procedure CAN_SCE_interrupt; external name 'CAN_SCE_interrupt';
procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
procedure TIM1_Break_interrupt; external name 'TIM1_Break_interrupt';
procedure TIM1_Update_interrupt; external name 'TIM1_Update_interrupt';
procedure TIM1_Trigger_and_Commutation_interrupts; external name 'TIM1_Trigger_and_Commutation_interrupts';
procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
procedure USB_wakeup_from_suspend_through_EXTI_line_interrupt; external name 'USB_wakeup_from_suspend_through_EXTI_line_interrupt';
procedure TIM8_Break_interrupt; external name 'TIM8_Break_interrupt';
procedure TIM8_Update_interrupt; external name 'TIM8_Update_interrupt';
procedure TIM8_Trigger_and_Commutation_interrupts; external name 'TIM8_Trigger_and_Commutation_interrupts';
procedure TIM8_Capture_Compare_interrupt; external name 'TIM8_Capture_Compare_interrupt';
procedure ADC3_global_interrupt; external name 'ADC3_global_interrupt';
procedure FSMC_global_interrupt; external name 'FSMC_global_interrupt';
procedure SDIO_global_interrupt; external name 'SDIO_global_interrupt';
procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
procedure DMA2_Channel4_and_DMA2_Channel5_global_interrupts; external name 'DMA2_Channel4_and_DMA2_Channel5_global_interrupts';
{$i cortexm3_start.inc}
procedure Vectors; assembler; nostackframe;
label interrupt_vectors;
asm
.section ".init.interrupt_vectors"
interrupt_vectors:
.long _stack_top
.long Startup
.long NMI_interrupt
.long Hardfault_interrupt
.long MemManage_interrupt
.long BusFault_interrupt
.long UsageFault_interrupt
.long 0
.long 0
.long 0
.long 0
.long SWI_interrupt
.long DebugMonitor_interrupt
.long 0
.long PendingSV_interrupt
.long SysTick_interrupt
.long Window_watchdog_interrupt
.long PVD_through_EXTI_Line_detection_interrupt
.long Tamper_interrupt
.long RTC_global_interrupt
.long Flash_global_interrupt
.long RCC_global_interrupt
.long EXTI_Line0_interrupt
.long EXTI_Line1_interrupt
.long EXTI_Line2_interrupt
.long EXTI_Line3_interrupt
.long EXTI_Line4_interrupt
.long DMA1_Channel1_global_interrupt
.long DMA1_Channel2_global_interrupt
.long DMA1_Channel3_global_interrupt
.long DMA1_Channel4_global_interrupt
.long DMA1_Channel5_global_interrupt
.long DMA1_Channel6_global_interrupt
.long DMA1_Channel7_global_interrupt
.long ADC1_and_ADC2_global_interrupt
.long USB_High_Priority_or_CAN_TX_interrupts
.long USB_Low_Priority_or_CAN_RX0_interrupts
.long CAN_RX1_interrupt
.long CAN_SCE_interrupt
.long EXTI_Line9_5_interrupts
.long TIM1_Break_interrupt
.long TIM1_Update_interrupt
.long TIM1_Trigger_and_Commutation_interrupts
.long TIM1_Capture_Compare_interrupt
.long TIM2_global_interrupt
.long TIM3_global_interrupt
.long TIM4_global_interrupt
.long I2C1_event_interrupt
.long I2C1_error_interrupt
.long I2C2_event_interrupt
.long I2C2_error_interrupt
.long SPI1_global_interrupt
.long SPI2_global_interrupt
.long USART1_global_interrupt
.long USART2_global_interrupt
.long USART3_global_interrupt
.long EXTI_Line15_10_interrupts
.long RTC_alarm_through_EXTI_line_interrupt
.long USB_wakeup_from_suspend_through_EXTI_line_interrupt
.long TIM8_Break_interrupt
.long TIM8_Update_interrupt
.long TIM8_Trigger_and_Commutation_interrupts
.long TIM8_Capture_Compare_interrupt
.long ADC3_global_interrupt
.long FSMC_global_interrupt
.long SDIO_global_interrupt
.long TIM5_global_interrupt
.long SPI3_global_interrupt
.long UART4_global_interrupt
.long UART5_global_interrupt
.long TIM6_global_interrupt
.long TIM7_global_interrupt
.long DMA2_Channel1_global_interrupt
.long DMA2_Channel2_global_interrupt
.long DMA2_Channel3_global_interrupt
.long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
.weak NMI_interrupt
.weak Hardfault_interrupt
.weak MemManage_interrupt
.weak BusFault_interrupt
.weak UsageFault_interrupt
.weak SWI_interrupt
.weak DebugMonitor_interrupt
.weak PendingSV_interrupt
.weak SysTick_interrupt
.weak Window_watchdog_interrupt
.weak PVD_through_EXTI_Line_detection_interrupt
.weak Tamper_interrupt
.weak RTC_global_interrupt
.weak Flash_global_interrupt
.weak RCC_global_interrupt
.weak EXTI_Line0_interrupt
.weak EXTI_Line1_interrupt
.weak EXTI_Line2_interrupt
.weak EXTI_Line3_interrupt
.weak EXTI_Line4_interrupt
.weak DMA1_Channel1_global_interrupt
.weak DMA1_Channel2_global_interrupt
.weak DMA1_Channel3_global_interrupt
.weak DMA1_Channel4_global_interrupt
.weak DMA1_Channel5_global_interrupt
.weak DMA1_Channel6_global_interrupt
.weak DMA1_Channel7_global_interrupt
.weak ADC1_and_ADC2_global_interrupt
.weak USB_High_Priority_or_CAN_TX_interrupts
.weak USB_Low_Priority_or_CAN_RX0_interrupts
.weak CAN_RX1_interrupt
.weak CAN_SCE_interrupt
.weak EXTI_Line9_5_interrupts
.weak TIM1_Break_interrupt
.weak TIM1_Update_interrupt
.weak TIM1_Trigger_and_Commutation_interrupts
.weak TIM1_Capture_Compare_interrupt
.weak TIM2_global_interrupt
.weak TIM3_global_interrupt
.weak TIM4_global_interrupt
.weak I2C1_event_interrupt
.weak I2C1_error_interrupt
.weak I2C2_event_interrupt
.weak I2C2_error_interrupt
.weak SPI1_global_interrupt
.weak SPI2_global_interrupt
.weak USART1_global_interrupt
.weak USART2_global_interrupt
.weak USART3_global_interrupt
.weak EXTI_Line15_10_interrupts
.weak RTC_alarm_through_EXTI_line_interrupt
.weak USB_wakeup_from_suspend_through_EXTI_line_interrupt
.weak TIM8_Break_interrupt
.weak TIM8_Update_interrupt
.weak TIM8_Trigger_and_Commutation_interrupts
.weak TIM8_Capture_Compare_interrupt
.weak ADC3_global_interrupt
.weak FSMC_global_interrupt
.weak SDIO_global_interrupt
.weak TIM5_global_interrupt
.weak SPI3_global_interrupt
.weak UART4_global_interrupt
.weak UART5_global_interrupt
.weak TIM6_global_interrupt
.weak TIM7_global_interrupt
.weak DMA2_Channel1_global_interrupt
.weak DMA2_Channel2_global_interrupt
.weak DMA2_Channel3_global_interrupt
.weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
.set NMI_interrupt, Startup
.set Hardfault_interrupt, Startup
.set MemManage_interrupt, Startup
.set BusFault_interrupt, Startup
.set UsageFault_interrupt, Startup
.set SWI_interrupt, Startup
.set DebugMonitor_interrupt, Startup
.set PendingSV_interrupt, Startup
.set SysTick_interrupt, Startup
.set Window_watchdog_interrupt, Startup
.set PVD_through_EXTI_Line_detection_interrupt, Startup
.set Tamper_interrupt, Startup
.set RTC_global_interrupt, Startup
.set Flash_global_interrupt, Startup
.set RCC_global_interrupt, Startup
.set EXTI_Line0_interrupt, Startup
.set EXTI_Line1_interrupt, Startup
.set EXTI_Line2_interrupt, Startup
.set EXTI_Line3_interrupt, Startup
.set EXTI_Line4_interrupt, Startup
.set DMA1_Channel1_global_interrupt, Startup
.set DMA1_Channel2_global_interrupt, Startup
.set DMA1_Channel3_global_interrupt, Startup
.set DMA1_Channel4_global_interrupt, Startup
.set DMA1_Channel5_global_interrupt, Startup
.set DMA1_Channel6_global_interrupt, Startup
.set DMA1_Channel7_global_interrupt, Startup
.set ADC1_and_ADC2_global_interrupt, Startup
.set USB_High_Priority_or_CAN_TX_interrupts, Startup
.set USB_Low_Priority_or_CAN_RX0_interrupts, Startup
.set CAN_RX1_interrupt, Startup
.set CAN_SCE_interrupt, Startup
.set EXTI_Line9_5_interrupts, Startup
.set TIM1_Break_interrupt, Startup
.set TIM1_Update_interrupt, Startup
.set TIM1_Trigger_and_Commutation_interrupts, Startup
.set TIM1_Capture_Compare_interrupt, Startup
.set TIM2_global_interrupt, Startup
.set TIM3_global_interrupt, Startup
.set TIM4_global_interrupt, Startup
.set I2C1_event_interrupt, Startup
.set I2C1_error_interrupt, Startup
.set I2C2_event_interrupt, Startup
.set I2C2_error_interrupt, Startup
.set SPI1_global_interrupt, Startup
.set SPI2_global_interrupt, Startup
.set USART1_global_interrupt, Startup
.set USART2_global_interrupt, Startup
.set USART3_global_interrupt, Startup
.set EXTI_Line15_10_interrupts, Startup
.set RTC_alarm_through_EXTI_line_interrupt, Startup
.set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup
.set TIM8_Break_interrupt, Startup
.set TIM8_Update_interrupt, Startup
.set TIM8_Trigger_and_Commutation_interrupts, Startup
.set TIM8_Capture_Compare_interrupt, Startup
.set ADC3_global_interrupt, Startup
.set FSMC_global_interrupt, Startup
.set SDIO_global_interrupt, Startup
.set TIM5_global_interrupt, Startup
.set SPI3_global_interrupt, Startup
.set UART4_global_interrupt, Startup
.set UART5_global_interrupt, Startup
.set TIM6_global_interrupt, Startup
.set TIM7_global_interrupt, Startup
.set DMA2_Channel1_global_interrupt, Startup
.set DMA2_Channel2_global_interrupt, Startup
.set DMA2_Channel3_global_interrupt, Startup
.set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup
.text
end;
end.

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rtl/embedded/arm/stm32f10x_ld.pp Normal file
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{
Register definitions and utility code for STM32F10x - Low Density
Created by Jeppe Johansen 2012 - jeppe@j-software.dk
}
unit stm32f10x_ld;
{$goto on}
{$define stm32f10x_ld}
interface
type
TBitvector32 = bitpacked array[0..31] of 0..1;
{$PACKRECORDS 2}
const
PeripheralBase = $40000000;
FSMCBase = $60000000;
APB1Base = PeripheralBase;
APB2Base = PeripheralBase+$10000;
AHBBase = PeripheralBase+$20000;
SCS_BASE = $E000E000;
{ FSMC }
FSMCBank1NOR1 = FSMCBase+$00000000;
FSMCBank1NOR2 = FSMCBase+$04000000;
FSMCBank1NOR3 = FSMCBase+$08000000;
FSMCBank1NOR4 = FSMCBase+$0C000000;
FSMCBank1PSRAM1 = FSMCBase+$00000000;
FSMCBank1PSRAM2 = FSMCBase+$04000000;
FSMCBank1PSRAM3 = FSMCBase+$08000000;
FSMCBank1PSRAM4 = FSMCBase+$0C000000;
FSMCBank2NAND1 = FSMCBase+$10000000;
FSMCBank3NAND2 = FSMCBase+$20000000;
FSMCBank4PCCARD = FSMCBase+$30000000;
type
TTimerRegisters = record
CR1, res1,
CR2, res2,
SMCR, res3,
DIER, res4,
SR, res5,
EGR, res,
CCMR1, res6,
CCMR2, res7,
CCER, res8,
CNT, res9,
PSC, res10,
ARR, res11,
RCR, res12,
CCR1, res13,
CCR2, res14,
CCR3, res15,
CCR4, res16,
BDTR, res17,
DCR, res18,
DMAR, res19: Word;
end;
TRTCRegisters = record
CRH, res1,
CRL, res2,
PRLH, res3,
PRLL, res4,
DIVH, res5,
DIVL, res6,
CNTH, res7,
CNTL, res8,
ALRH, res9,
ALRL, res10: Word;
end;
TIWDGRegisters = record
KR, res1,
PR, res2,
RLR, res3,
SR, res4: word;
end;
TWWDGRegisters = record
CR, res2,
CFR, res3,
SR, res4: word;
end;
TSPIRegisters = record
CR1, res1,
CR2, res2,
SR, res3,
DR, res4,
CRCPR, res5,
RXCRCR, res6,
TXCRCR, res7,
I2SCFGR, res8,
I2SPR, res9: Word;
end;
TUSARTRegisters = record
SR, res1,
DR, res2,
BRR, res3,
CR1, res4,
CR2, res5,
CR3, res6,
GTPR, res7: Word;
end;
TI2CRegisters = record
CR1, res1,
CR2, res2,
OAR1, res3,
OAR2, res4,
DR, res5,
SR1, res6,
SR2, res7,
CCR, res8: word;
TRISE: byte;
end;
TUSBRegisters = record
EPR: array[0..7] of longword;
res: array[0..7] of longword;
CNTR, res1,
ISTR, res2,
FNR, res3: Word;
DADDR: byte; res4: word; res5: byte;
BTABLE: Word;
end;
TUSBMem = packed array[0..511] of byte;
TCANMailbox = record
IR,
DTR,
DLR,
DHR: longword;
end;
TCANRegisters = record
MCR,
MSR,
TSR,
RF0R,
RF1R,
IER,
ESR,
BTR: longword;
res5: array[$020..$17F] of byte;
TX: array[0..2] of TCANMailbox;
RX: array[0..2] of TCANMailbox;
res6: array[$1D0..$1FF] of byte;
FMR,
FM1R,
res9: longword;
FS1R, res10: word;
res11: longword;
FFA1R, res12: word;
res13: longword;
FA1R, res14: word;
res15: array[$220..$23F] of byte;
FOR1,
FOR2: longword;
FB: array[1..13] of array[1..2] of longword;
end;
TBKPRegisters = record
DR: array[1..10] of record data, res: word; end;
RTCCR,
CR,
CSR,
res1,res2: longword;
DR2: array[11..42] of record data, res: word; end;
end;
TPwrRegisters = record
CR, res: word;
CSR: Word;
end;
TDACRegisters = record
CR,
SWTRIGR: longword;
DHR12R1, res2,
DHR12L1, res3,
DHR8R1, res4,
DHR12R2, res5,
DHR12L2, res6,
DHR8R2, res7: word;
DHR12RD,
DHR12LD: longword;
DHR8RD, res8,
DOR1, res9,
DOR2, res10: Word;
end;
TAFIORegisters = record
EVCR,
MAPR: longword;
EXTICR: array[0..3] of longword;
end;
TEXTIRegisters = record
IMR,
EMR,
RTSR,
FTSR,
SWIER,
PR: longword;
end;
TPortRegisters = record
CRL,
CRH,
IDR,
ODR,
BSRR,
BRR,
LCKR: longword;
end;
TADCRegisters = record
SR,
CR1,
CR2,
SMPR1,
SMPR2: longword;
JOFR1, res2,
JOFR2, res3,
JOFR3, res4,
JOFR4, res5,
HTR, res6,
LTR, res7: word;
SQR1,
SQR2,
SQR3,
JSQR: longword;
JDR1, res8,
JDR2, res9,
JDR3, res10,
JDR4, res11: Word;
DR: longword;
end;
TSDIORegisters = record
POWER,
CLKCR,
ARG: longword;
CMD, res3,
RESPCMD, res4: Word;
RESP1,
RESP2,
RESP3,
RESP4,
DTIMER,
DLEN: longword;
DCTRL, res5: word;
DCOUNT,
STA,
ICR,
MASK,
FIFOCNT,
FIFO: longword;
end;
TDMAChannel = record
CCR, res1,
CNDTR, res2: word;
CPAR,
CMAR,
res: longword;
end;
TDMARegisters = record
ISR,
IFCR: longword;
Channel: array[0..7] of TDMAChannel;
end;
TRCCRegisters = record
CR,
CFGR,
CIR,
APB2RSTR,
APB1RSTR,
AHBENR,
APB2ENR,
APB1ENR,
BDCR,
CSR: longword;
end;
TCRCRegisters = record
DR: longword;
IDR: byte; res1: word; res2: byte;
CR: byte;
end;
TFSMCRegisters = record
nothingyet: byte;
end;
TFlashRegisters = record
ACR,
KEYR,
OPTKEYR,
SR,
CR,
AR,
res,
OBR,
WRPR: longword;
end;
TNVICRegisters = record
ISER: array[0..7] of longword;
reserved0: array[0..23] of longword;
ICER: array[0..7] of longword;
reserved1: array[0..23] of longword;
ISPR: array[0..7] of longword;
reserved2: array[0..23] of longword;
ICPR: array[0..7] of longword;
reserved3: array[0..23] of longword;
IABR: array[0..7] of longword;
reserved4: array[0..55] of longword;
IP: array[0..239] of longword;
reserved5: array[0..643] of longword;
STIR: longword;
end;
TSCBRegisters = record
CPUID, {!< CPU ID Base Register }
ICSR, {!< Interrupt Control State Register }
VTOR, {!< Vector Table Offset Register }
AIRCR, {!< Application Interrupt / Reset Control Register }
SCR, {!< System Control Register }
CCR: longword; {!< Configuration Control Register }
SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
SHCSR, {!< System Handler Control and State Register }
CFSR, {!< Configurable Fault Status Register }
HFSR, {!< Hard Fault Status Register }
DFSR, {!< Debug Fault Status Register }
MMFAR, {!< Mem Manage Address Register }
BFAR, {!< Bus Fault Address Register }
AFSR: longword; {!< Auxiliary Fault Status Register }
PFR: array[0..1] of longword; {!< Processor Feature Register }
DFR, {!< Debug Feature Register }
ADR: longword; {!< Auxiliary Feature Register }
MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
ISAR: array[0..4] of longword; {!< ISA Feature Register }
end;
TSysTickRegisters = record
Ctrl,
Load,
Val,
Calib: longword;
end;
{$ALIGN 2}
var
{ Timers }
Timer1: TTimerRegisters absolute (APB2Base+$2C00);
Timer2: TTimerRegisters absolute (APB1Base+$0000);
Timer3: TTimerRegisters absolute (APB1Base+$0400);
Timer4: TTimerRegisters absolute (APB1Base+$0800);
Timer5: TTimerRegisters absolute (APB1Base+$0C00);
Timer6: TTimerRegisters absolute (APB1Base+$1000);
Timer7: TTimerRegisters absolute (APB1Base+$1400);
Timer8: TTimerRegisters absolute (APB2Base+$3400);
{ RTC }
RTC: TRTCRegisters absolute (APB1Base+$2800);
{ WDG }
WWDG: TWWDGRegisters absolute (APB1Base+$2C00);
IWDG: TIWDGRegisters absolute (APB1Base+$3000);
{ SPI }
SPI1: TSPIRegisters absolute (APB2Base+$3000);
SPI2: TSPIRegisters absolute (APB1Base+$3800);
SPI3: TSPIRegisters absolute (APB1Base+$3C00);
{ USART/UART }
USART1: TUSARTRegisters absolute (APB2Base+$3800);
USART2: TUSARTRegisters absolute (APB1Base+$4400);
USART3: TUSARTRegisters absolute (APB1Base+$4800);
UART4: TUSARTRegisters absolute (APB1Base+$4C00);
UART5: TUSARTRegisters absolute (APB1Base+$5000);
{ I2C }
I2C1: TI2CRegisters absolute (APB1Base+$5400);
I2C2: TI2CRegisters absolute (APB1Base+$5800);
{ USB }
USB: TUSBRegisters absolute (APB1Base+$5C00);
USBMem: TUSBMem absolute (APB1Base+$6000);
{ CAN }
CAN: TCANRegisters absolute (APB1Base+$6800);
{ BKP }
BKP: TBKPRegisters absolute (APB1Base+$6C00);
{ PWR }
PWR: TPwrRegisters absolute (APB1Base+$7000);
{ DAC }
DAC: TDACRegisters absolute (APB1Base+$7400);
{ GPIO }
AFIO: TAFIORegisters absolute (APB2Base+$0);
EXTI: TEXTIRegisters absolute (APB2Base+$0400);
PortA: TPortRegisters absolute (APB2Base+$0800);
PortB: TPortRegisters absolute (APB2Base+$0C00);
PortC: TPortRegisters absolute (APB2Base+$1000);
PortD: TPortRegisters absolute (APB2Base+$1400);
PortE: TPortRegisters absolute (APB2Base+$1800);
PortF: TPortRegisters absolute (APB2Base+$1C00);
PortG: TPortRegisters absolute (APB2Base+$2000);
{ ADC }
ADC1: TADCRegisters absolute (APB2Base+$2400);
ADC2: TADCRegisters absolute (APB2Base+$2800);
ADC3: TADCRegisters absolute (APB2Base+$3C00);
{ SDIO }
SDIO: TSDIORegisters absolute (APB2Base+$8000);
{ DMA }
DMA1: TDMARegisters absolute (AHBBase+$0000);
DMA2: TDMARegisters absolute (AHBBase+$0400);
{ RCC }
RCC: TRCCRegisters absolute (AHBBase+$1000);
{ Flash }
Flash: TFlashRegisters absolute (AHBBase+$2000);
{ CRC }
CRC: TCRCRegisters absolute (AHBBase+$3000);
{ SCB }
SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
{ SysTick }
SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
{ NVIC }
NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
implementation
procedure NMI_interrupt; external name 'NMI_interrupt';
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
procedure MemManage_interrupt; external name 'MemManage_interrupt';
procedure BusFault_interrupt; external name 'BusFault_interrupt';
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
procedure SWI_interrupt; external name 'SWI_interrupt';
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
procedure SysTick_interrupt; external name 'SysTick_interrupt';
procedure Window_watchdog_interrupt; external name 'Window_watchdog_interrupt';
procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
procedure Tamper_interrupt; external name 'Tamper_interrupt';
procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
procedure USB_High_Priority_or_CAN_TX_interrupts; external name 'USB_High_Priority_or_CAN_TX_interrupts';
procedure USB_Low_Priority_or_CAN_RX0_interrupts; external name 'USB_Low_Priority_or_CAN_RX0_interrupts';
procedure CAN_RX1_interrupt; external name 'CAN_RX1_interrupt';
procedure CAN_SCE_interrupt; external name 'CAN_SCE_interrupt';
procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
procedure TIM1_Break_interrupt; external name 'TIM1_Break_interrupt';
procedure TIM1_Update_interrupt; external name 'TIM1_Update_interrupt';
procedure TIM1_Trigger_and_Commutation_interrupts; external name 'TIM1_Trigger_and_Commutation_interrupts';
procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
procedure USB_wakeup_from_suspend_through_EXTI_line_interrupt; external name 'USB_wakeup_from_suspend_through_EXTI_line_interrupt';
procedure TIM8_Break_interrupt; external name 'TIM8_Break_interrupt';
procedure TIM8_Update_interrupt; external name 'TIM8_Update_interrupt';
procedure TIM8_Trigger_and_Commutation_interrupts; external name 'TIM8_Trigger_and_Commutation_interrupts';
procedure TIM8_Capture_Compare_interrupt; external name 'TIM8_Capture_Compare_interrupt';
procedure ADC3_global_interrupt; external name 'ADC3_global_interrupt';
procedure FSMC_global_interrupt; external name 'FSMC_global_interrupt';
procedure SDIO_global_interrupt; external name 'SDIO_global_interrupt';
procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
procedure DMA2_Channel4_and_DMA2_Channel5_global_interrupts; external name 'DMA2_Channel4_and_DMA2_Channel5_global_interrupts';
{$i cortexm3_start.inc}
procedure Vectors; assembler; nostackframe;
label interrupt_vectors;
asm
.section ".init.interrupt_vectors"
interrupt_vectors:
.long _stack_top
.long Startup
.long NMI_interrupt
.long Hardfault_interrupt
.long MemManage_interrupt
.long BusFault_interrupt
.long UsageFault_interrupt
.long 0
.long 0
.long 0
.long 0
.long SWI_interrupt
.long DebugMonitor_interrupt
.long 0
.long PendingSV_interrupt
.long SysTick_interrupt
.long Window_watchdog_interrupt
.long PVD_through_EXTI_Line_detection_interrupt
.long Tamper_interrupt
.long RTC_global_interrupt
.long Flash_global_interrupt
.long RCC_global_interrupt
.long EXTI_Line0_interrupt
.long EXTI_Line1_interrupt
.long EXTI_Line2_interrupt
.long EXTI_Line3_interrupt
.long EXTI_Line4_interrupt
.long DMA1_Channel1_global_interrupt
.long DMA1_Channel2_global_interrupt
.long DMA1_Channel3_global_interrupt
.long DMA1_Channel4_global_interrupt
.long DMA1_Channel5_global_interrupt
.long DMA1_Channel6_global_interrupt
.long DMA1_Channel7_global_interrupt
.long ADC1_and_ADC2_global_interrupt
.long USB_High_Priority_or_CAN_TX_interrupts
.long USB_Low_Priority_or_CAN_RX0_interrupts
.long CAN_RX1_interrupt
.long CAN_SCE_interrupt
.long EXTI_Line9_5_interrupts
.long TIM1_Break_interrupt
.long TIM1_Update_interrupt
.long TIM1_Trigger_and_Commutation_interrupts
.long TIM1_Capture_Compare_interrupt
.long TIM2_global_interrupt
.long TIM3_global_interrupt
.long TIM4_global_interrupt
.long I2C1_event_interrupt
.long I2C1_error_interrupt
.long I2C2_event_interrupt
.long I2C2_error_interrupt
.long SPI1_global_interrupt
.long SPI2_global_interrupt
.long USART1_global_interrupt
.long USART2_global_interrupt
.long USART3_global_interrupt
.long EXTI_Line15_10_interrupts
.long RTC_alarm_through_EXTI_line_interrupt
.long USB_wakeup_from_suspend_through_EXTI_line_interrupt
.long TIM8_Break_interrupt
.long TIM8_Update_interrupt
.long TIM8_Trigger_and_Commutation_interrupts
.long TIM8_Capture_Compare_interrupt
.long ADC3_global_interrupt
.long FSMC_global_interrupt
.long SDIO_global_interrupt
.long TIM5_global_interrupt
.long SPI3_global_interrupt
.long UART4_global_interrupt
.long UART5_global_interrupt
.long TIM6_global_interrupt
.long TIM7_global_interrupt
.long DMA2_Channel1_global_interrupt
.long DMA2_Channel2_global_interrupt
.long DMA2_Channel3_global_interrupt
.long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
.weak NMI_interrupt
.weak Hardfault_interrupt
.weak MemManage_interrupt
.weak BusFault_interrupt
.weak UsageFault_interrupt
.weak SWI_interrupt
.weak DebugMonitor_interrupt
.weak PendingSV_interrupt
.weak SysTick_interrupt
.weak Window_watchdog_interrupt
.weak PVD_through_EXTI_Line_detection_interrupt
.weak Tamper_interrupt
.weak RTC_global_interrupt
.weak Flash_global_interrupt
.weak RCC_global_interrupt
.weak EXTI_Line0_interrupt
.weak EXTI_Line1_interrupt
.weak EXTI_Line2_interrupt
.weak EXTI_Line3_interrupt
.weak EXTI_Line4_interrupt
.weak DMA1_Channel1_global_interrupt
.weak DMA1_Channel2_global_interrupt
.weak DMA1_Channel3_global_interrupt
.weak DMA1_Channel4_global_interrupt
.weak DMA1_Channel5_global_interrupt
.weak DMA1_Channel6_global_interrupt
.weak DMA1_Channel7_global_interrupt
.weak ADC1_and_ADC2_global_interrupt
.weak USB_High_Priority_or_CAN_TX_interrupts
.weak USB_Low_Priority_or_CAN_RX0_interrupts
.weak CAN_RX1_interrupt
.weak CAN_SCE_interrupt
.weak EXTI_Line9_5_interrupts
.weak TIM1_Break_interrupt
.weak TIM1_Update_interrupt
.weak TIM1_Trigger_and_Commutation_interrupts
.weak TIM1_Capture_Compare_interrupt
.weak TIM2_global_interrupt
.weak TIM3_global_interrupt
.weak TIM4_global_interrupt
.weak I2C1_event_interrupt
.weak I2C1_error_interrupt
.weak I2C2_event_interrupt
.weak I2C2_error_interrupt
.weak SPI1_global_interrupt
.weak SPI2_global_interrupt
.weak USART1_global_interrupt
.weak USART2_global_interrupt
.weak USART3_global_interrupt
.weak EXTI_Line15_10_interrupts
.weak RTC_alarm_through_EXTI_line_interrupt
.weak USB_wakeup_from_suspend_through_EXTI_line_interrupt
.weak TIM8_Break_interrupt
.weak TIM8_Update_interrupt
.weak TIM8_Trigger_and_Commutation_interrupts
.weak TIM8_Capture_Compare_interrupt
.weak ADC3_global_interrupt
.weak FSMC_global_interrupt
.weak SDIO_global_interrupt
.weak TIM5_global_interrupt
.weak SPI3_global_interrupt
.weak UART4_global_interrupt
.weak UART5_global_interrupt
.weak TIM6_global_interrupt
.weak TIM7_global_interrupt
.weak DMA2_Channel1_global_interrupt
.weak DMA2_Channel2_global_interrupt
.weak DMA2_Channel3_global_interrupt
.weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
.set NMI_interrupt, Startup
.set Hardfault_interrupt, Startup
.set MemManage_interrupt, Startup
.set BusFault_interrupt, Startup
.set UsageFault_interrupt, Startup
.set SWI_interrupt, Startup
.set DebugMonitor_interrupt, Startup
.set PendingSV_interrupt, Startup
.set SysTick_interrupt, Startup
.set Window_watchdog_interrupt, Startup
.set PVD_through_EXTI_Line_detection_interrupt, Startup
.set Tamper_interrupt, Startup
.set RTC_global_interrupt, Startup
.set Flash_global_interrupt, Startup
.set RCC_global_interrupt, Startup
.set EXTI_Line0_interrupt, Startup
.set EXTI_Line1_interrupt, Startup
.set EXTI_Line2_interrupt, Startup
.set EXTI_Line3_interrupt, Startup
.set EXTI_Line4_interrupt, Startup
.set DMA1_Channel1_global_interrupt, Startup
.set DMA1_Channel2_global_interrupt, Startup
.set DMA1_Channel3_global_interrupt, Startup
.set DMA1_Channel4_global_interrupt, Startup
.set DMA1_Channel5_global_interrupt, Startup
.set DMA1_Channel6_global_interrupt, Startup
.set DMA1_Channel7_global_interrupt, Startup
.set ADC1_and_ADC2_global_interrupt, Startup
.set USB_High_Priority_or_CAN_TX_interrupts, Startup
.set USB_Low_Priority_or_CAN_RX0_interrupts, Startup
.set CAN_RX1_interrupt, Startup
.set CAN_SCE_interrupt, Startup
.set EXTI_Line9_5_interrupts, Startup
.set TIM1_Break_interrupt, Startup
.set TIM1_Update_interrupt, Startup
.set TIM1_Trigger_and_Commutation_interrupts, Startup
.set TIM1_Capture_Compare_interrupt, Startup
.set TIM2_global_interrupt, Startup
.set TIM3_global_interrupt, Startup
.set TIM4_global_interrupt, Startup
.set I2C1_event_interrupt, Startup
.set I2C1_error_interrupt, Startup
.set I2C2_event_interrupt, Startup
.set I2C2_error_interrupt, Startup
.set SPI1_global_interrupt, Startup
.set SPI2_global_interrupt, Startup
.set USART1_global_interrupt, Startup
.set USART2_global_interrupt, Startup
.set USART3_global_interrupt, Startup
.set EXTI_Line15_10_interrupts, Startup
.set RTC_alarm_through_EXTI_line_interrupt, Startup
.set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup
.set TIM8_Break_interrupt, Startup
.set TIM8_Update_interrupt, Startup
.set TIM8_Trigger_and_Commutation_interrupts, Startup
.set TIM8_Capture_Compare_interrupt, Startup
.set ADC3_global_interrupt, Startup
.set FSMC_global_interrupt, Startup
.set SDIO_global_interrupt, Startup
.set TIM5_global_interrupt, Startup
.set SPI3_global_interrupt, Startup
.set UART4_global_interrupt, Startup
.set UART5_global_interrupt, Startup
.set TIM6_global_interrupt, Startup
.set TIM7_global_interrupt, Startup
.set DMA2_Channel1_global_interrupt, Startup
.set DMA2_Channel2_global_interrupt, Startup
.set DMA2_Channel3_global_interrupt, Startup
.set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup
.text
end;
end.

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rtl/embedded/arm/stm32f10x_md.pp Normal file
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{
Register definitions and utility code for STM32F10x - Medium density
Created by Jeppe Johansen 2012 - jeppe@j-software.dk
}
unit stm32f10x_md;
{$goto on}
{$define stm32f10x_md}
interface
type
TBitvector32 = bitpacked array[0..31] of 0..1;
{$PACKRECORDS 2}
const
PeripheralBase = $40000000;
FSMCBase = $60000000;
APB1Base = PeripheralBase;
APB2Base = PeripheralBase+$10000;
AHBBase = PeripheralBase+$20000;
SCS_BASE = $E000E000;
{ FSMC }
FSMCBank1NOR1 = FSMCBase+$00000000;
FSMCBank1NOR2 = FSMCBase+$04000000;
FSMCBank1NOR3 = FSMCBase+$08000000;
FSMCBank1NOR4 = FSMCBase+$0C000000;
FSMCBank1PSRAM1 = FSMCBase+$00000000;
FSMCBank1PSRAM2 = FSMCBase+$04000000;
FSMCBank1PSRAM3 = FSMCBase+$08000000;
FSMCBank1PSRAM4 = FSMCBase+$0C000000;
FSMCBank2NAND1 = FSMCBase+$10000000;
FSMCBank3NAND2 = FSMCBase+$20000000;
FSMCBank4PCCARD = FSMCBase+$30000000;
type
TTimerRegisters = record
CR1, res1,
CR2, res2,
SMCR, res3,
DIER, res4,
SR, res5,
EGR, res,
CCMR1, res6,
CCMR2, res7,
CCER, res8,
CNT, res9,
PSC, res10,
ARR, res11,
RCR, res12,
CCR1, res13,
CCR2, res14,
CCR3, res15,
CCR4, res16,
BDTR, res17,
DCR, res18,
DMAR, res19: Word;
end;
TRTCRegisters = record
CRH, res1,
CRL, res2,
PRLH, res3,
PRLL, res4,
DIVH, res5,
DIVL, res6,
CNTH, res7,
CNTL, res8,
ALRH, res9,
ALRL, res10: Word;
end;
TIWDGRegisters = record
KR, res1,
PR, res2,
RLR, res3,
SR, res4: word;
end;
TWWDGRegisters = record
CR, res2,
CFR, res3,
SR, res4: word;
end;
TSPIRegisters = record
CR1, res1,
CR2, res2,
SR, res3,
DR, res4,
CRCPR, res5,
RXCRCR, res6,
TXCRCR, res7,
I2SCFGR, res8,
I2SPR, res9: Word;
end;
TUSARTRegisters = record
SR, res1,
DR, res2,
BRR, res3,
CR1, res4,
CR2, res5,
CR3, res6,
GTPR, res7: Word;
end;
TI2CRegisters = record
CR1, res1,
CR2, res2,
OAR1, res3,
OAR2, res4,
DR, res5,
SR1, res6,
SR2, res7,
CCR, res8: word;
TRISE: byte;
end;
TUSBRegisters = record
EPR: array[0..7] of longword;
res: array[0..7] of longword;
CNTR, res1,
ISTR, res2,
FNR, res3: Word;
DADDR: byte; res4: word; res5: byte;
BTABLE: Word;
end;
TUSBMem = packed array[0..511] of byte;
TCANMailbox = record
IR,
DTR,
DLR,
DHR: longword;
end;
TCANRegisters = record
MCR,
MSR,
TSR,
RF0R,
RF1R,
IER,
ESR,
BTR: longword;
res5: array[$020..$17F] of byte;
TX: array[0..2] of TCANMailbox;
RX: array[0..2] of TCANMailbox;
res6: array[$1D0..$1FF] of byte;
FMR,
FM1R,
res9: longword;
FS1R, res10: word;
res11: longword;
FFA1R, res12: word;
res13: longword;
FA1R, res14: word;
res15: array[$220..$23F] of byte;
FOR1,
FOR2: longword;
FB: array[1..13] of array[1..2] of longword;
end;
TBKPRegisters = record
DR: array[1..10] of record data, res: word; end;
RTCCR,
CR,
CSR,
res1,res2: longword;
DR2: array[11..42] of record data, res: word; end;
end;
TPwrRegisters = record
CR, res: word;
CSR: Word;
end;
TDACRegisters = record
CR,
SWTRIGR: longword;
DHR12R1, res2,
DHR12L1, res3,
DHR8R1, res4,
DHR12R2, res5,
DHR12L2, res6,
DHR8R2, res7: word;
DHR12RD,
DHR12LD: longword;
DHR8RD, res8,
DOR1, res9,
DOR2, res10: Word;
end;
TAFIORegisters = record
EVCR,
MAPR: longword;
EXTICR: array[0..3] of longword;
end;
TEXTIRegisters = record
IMR,
EMR,
RTSR,
FTSR,
SWIER,
PR: longword;
end;
TPortRegisters = record
CRL,
CRH,
IDR,
ODR,
BSRR,
BRR,
LCKR: longword;
end;
TADCRegisters = record
SR,
CR1,
CR2,
SMPR1,
SMPR2: longword;
JOFR1, res2,
JOFR2, res3,
JOFR3, res4,
JOFR4, res5,
HTR, res6,
LTR, res7: word;
SQR1,
SQR2,
SQR3,
JSQR: longword;
JDR1, res8,
JDR2, res9,
JDR3, res10,
JDR4, res11: Word;
DR: longword;
end;
TSDIORegisters = record
POWER,
CLKCR,
ARG: longword;
CMD, res3,
RESPCMD, res4: Word;
RESP1,
RESP2,
RESP3,
RESP4,
DTIMER,
DLEN: longword;
DCTRL, res5: word;
DCOUNT,
STA,
ICR,
MASK,
FIFOCNT,
FIFO: longword;
end;
TDMAChannel = record
CCR, res1,
CNDTR, res2: word;
CPAR,
CMAR,
res: longword;
end;
TDMARegisters = record
ISR,
IFCR: longword;
Channel: array[0..7] of TDMAChannel;
end;
TRCCRegisters = record
CR,
CFGR,
CIR,
APB2RSTR,
APB1RSTR,
AHBENR,
APB2ENR,
APB1ENR,
BDCR,
CSR: longword;
end;
TCRCRegisters = record
DR: longword;
IDR: byte; res1: word; res2: byte;
CR: byte;
end;
TFSMCRegisters = record
nothingyet: byte;
end;
TFlashRegisters = record
ACR,
KEYR,
OPTKEYR,
SR,
CR,
AR,
res,
OBR,
WRPR: longword;
end;
TNVICRegisters = record
ISER: array[0..7] of longword;
reserved0: array[0..23] of longword;
ICER: array[0..7] of longword;
reserved1: array[0..23] of longword;
ISPR: array[0..7] of longword;
reserved2: array[0..23] of longword;
ICPR: array[0..7] of longword;
reserved3: array[0..23] of longword;
IABR: array[0..7] of longword;
reserved4: array[0..55] of longword;
IP: array[0..239] of longword;
reserved5: array[0..643] of longword;
STIR: longword;
end;
TSCBRegisters = record
CPUID, {!< CPU ID Base Register }
ICSR, {!< Interrupt Control State Register }
VTOR, {!< Vector Table Offset Register }
AIRCR, {!< Application Interrupt / Reset Control Register }
SCR, {!< System Control Register }
CCR: longword; {!< Configuration Control Register }
SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
SHCSR, {!< System Handler Control and State Register }
CFSR, {!< Configurable Fault Status Register }
HFSR, {!< Hard Fault Status Register }
DFSR, {!< Debug Fault Status Register }
MMFAR, {!< Mem Manage Address Register }
BFAR, {!< Bus Fault Address Register }
AFSR: longword; {!< Auxiliary Fault Status Register }
PFR: array[0..1] of longword; {!< Processor Feature Register }
DFR, {!< Debug Feature Register }
ADR: longword; {!< Auxiliary Feature Register }
MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
ISAR: array[0..4] of longword; {!< ISA Feature Register }
end;
TSysTickRegisters = record
Ctrl,
Load,
Val,
Calib: longword;
end;
{$ALIGN 2}
var
{ Timers }
Timer1: TTimerRegisters absolute (APB2Base+$2C00);
Timer2: TTimerRegisters absolute (APB1Base+$0000);
Timer3: TTimerRegisters absolute (APB1Base+$0400);
Timer4: TTimerRegisters absolute (APB1Base+$0800);
Timer5: TTimerRegisters absolute (APB1Base+$0C00);
Timer6: TTimerRegisters absolute (APB1Base+$1000);
Timer7: TTimerRegisters absolute (APB1Base+$1400);
Timer8: TTimerRegisters absolute (APB2Base+$3400);
{ RTC }
RTC: TRTCRegisters absolute (APB1Base+$2800);
{ WDG }
WWDG: TWWDGRegisters absolute (APB1Base+$2C00);
IWDG: TIWDGRegisters absolute (APB1Base+$3000);
{ SPI }
SPI1: TSPIRegisters absolute (APB2Base+$3000);
SPI2: TSPIRegisters absolute (APB1Base+$3800);
SPI3: TSPIRegisters absolute (APB1Base+$3C00);
{ USART/UART }
USART1: TUSARTRegisters absolute (APB2Base+$3800);
USART2: TUSARTRegisters absolute (APB1Base+$4400);
USART3: TUSARTRegisters absolute (APB1Base+$4800);
UART4: TUSARTRegisters absolute (APB1Base+$4C00);
UART5: TUSARTRegisters absolute (APB1Base+$5000);
{ I2C }
I2C1: TI2CRegisters absolute (APB1Base+$5400);
I2C2: TI2CRegisters absolute (APB1Base+$5800);
{ USB }
USB: TUSBRegisters absolute (APB1Base+$5C00);
USBMem: TUSBMem absolute (APB1Base+$6000);
{ CAN }
CAN: TCANRegisters absolute (APB1Base+$6800);
{ BKP }
BKP: TBKPRegisters absolute (APB1Base+$6C00);
{ PWR }
PWR: TPwrRegisters absolute (APB1Base+$7000);
{ DAC }
DAC: TDACRegisters absolute (APB1Base+$7400);
{ GPIO }
AFIO: TAFIORegisters absolute (APB2Base+$0);
EXTI: TEXTIRegisters absolute (APB2Base+$0400);
PortA: TPortRegisters absolute (APB2Base+$0800);
PortB: TPortRegisters absolute (APB2Base+$0C00);
PortC: TPortRegisters absolute (APB2Base+$1000);
PortD: TPortRegisters absolute (APB2Base+$1400);
PortE: TPortRegisters absolute (APB2Base+$1800);
PortF: TPortRegisters absolute (APB2Base+$1C00);
PortG: TPortRegisters absolute (APB2Base+$2000);
{ ADC }
ADC1: TADCRegisters absolute (APB2Base+$2400);
ADC2: TADCRegisters absolute (APB2Base+$2800);
ADC3: TADCRegisters absolute (APB2Base+$3C00);
{ SDIO }
SDIO: TSDIORegisters absolute (APB2Base+$8000);
{ DMA }
DMA1: TDMARegisters absolute (AHBBase+$0000);
DMA2: TDMARegisters absolute (AHBBase+$0400);
{ RCC }
RCC: TRCCRegisters absolute (AHBBase+$1000);
{ Flash }
Flash: TFlashRegisters absolute (AHBBase+$2000);
{ CRC }
CRC: TCRCRegisters absolute (AHBBase+$3000);
{ SCB }
SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
{ SysTick }
SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
{ NVIC }
NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
implementation
procedure NMI_interrupt; external name 'NMI_interrupt';
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
procedure MemManage_interrupt; external name 'MemManage_interrupt';
procedure BusFault_interrupt; external name 'BusFault_interrupt';
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
procedure SWI_interrupt; external name 'SWI_interrupt';
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
procedure SysTick_interrupt; external name 'SysTick_interrupt';
procedure Window_watchdog_interrupt; external name 'Window_watchdog_interrupt';
procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
procedure Tamper_interrupt; external name 'Tamper_interrupt';
procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
procedure USB_High_Priority_or_CAN_TX_interrupts; external name 'USB_High_Priority_or_CAN_TX_interrupts';
procedure USB_Low_Priority_or_CAN_RX0_interrupts; external name 'USB_Low_Priority_or_CAN_RX0_interrupts';
procedure CAN_RX1_interrupt; external name 'CAN_RX1_interrupt';
procedure CAN_SCE_interrupt; external name 'CAN_SCE_interrupt';
procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
procedure TIM1_Break_interrupt; external name 'TIM1_Break_interrupt';
procedure TIM1_Update_interrupt; external name 'TIM1_Update_interrupt';
procedure TIM1_Trigger_and_Commutation_interrupts; external name 'TIM1_Trigger_and_Commutation_interrupts';
procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
procedure USB_wakeup_from_suspend_through_EXTI_line_interrupt; external name 'USB_wakeup_from_suspend_through_EXTI_line_interrupt';
procedure TIM8_Break_interrupt; external name 'TIM8_Break_interrupt';
procedure TIM8_Update_interrupt; external name 'TIM8_Update_interrupt';
procedure TIM8_Trigger_and_Commutation_interrupts; external name 'TIM8_Trigger_and_Commutation_interrupts';
procedure TIM8_Capture_Compare_interrupt; external name 'TIM8_Capture_Compare_interrupt';
procedure ADC3_global_interrupt; external name 'ADC3_global_interrupt';
procedure FSMC_global_interrupt; external name 'FSMC_global_interrupt';
procedure SDIO_global_interrupt; external name 'SDIO_global_interrupt';
procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
procedure DMA2_Channel4_and_DMA2_Channel5_global_interrupts; external name 'DMA2_Channel4_and_DMA2_Channel5_global_interrupts';
{$i cortexm3_start.inc}
procedure Vectors; assembler; nostackframe;
label interrupt_vectors;
asm
.section ".init.interrupt_vectors"
interrupt_vectors:
.long _stack_top
.long Startup
.long NMI_interrupt
.long Hardfault_interrupt
.long MemManage_interrupt
.long BusFault_interrupt
.long UsageFault_interrupt
.long 0
.long 0
.long 0
.long 0
.long SWI_interrupt
.long DebugMonitor_interrupt
.long 0
.long PendingSV_interrupt
.long SysTick_interrupt
.long Window_watchdog_interrupt
.long PVD_through_EXTI_Line_detection_interrupt
.long Tamper_interrupt
.long RTC_global_interrupt
.long Flash_global_interrupt
.long RCC_global_interrupt
.long EXTI_Line0_interrupt
.long EXTI_Line1_interrupt
.long EXTI_Line2_interrupt
.long EXTI_Line3_interrupt
.long EXTI_Line4_interrupt
.long DMA1_Channel1_global_interrupt
.long DMA1_Channel2_global_interrupt
.long DMA1_Channel3_global_interrupt
.long DMA1_Channel4_global_interrupt
.long DMA1_Channel5_global_interrupt
.long DMA1_Channel6_global_interrupt
.long DMA1_Channel7_global_interrupt
.long ADC1_and_ADC2_global_interrupt
.long USB_High_Priority_or_CAN_TX_interrupts
.long USB_Low_Priority_or_CAN_RX0_interrupts
.long CAN_RX1_interrupt
.long CAN_SCE_interrupt
.long EXTI_Line9_5_interrupts
.long TIM1_Break_interrupt
.long TIM1_Update_interrupt
.long TIM1_Trigger_and_Commutation_interrupts
.long TIM1_Capture_Compare_interrupt
.long TIM2_global_interrupt
.long TIM3_global_interrupt
.long TIM4_global_interrupt
.long I2C1_event_interrupt
.long I2C1_error_interrupt
.long I2C2_event_interrupt
.long I2C2_error_interrupt
.long SPI1_global_interrupt
.long SPI2_global_interrupt
.long USART1_global_interrupt
.long USART2_global_interrupt
.long USART3_global_interrupt
.long EXTI_Line15_10_interrupts
.long RTC_alarm_through_EXTI_line_interrupt
.long USB_wakeup_from_suspend_through_EXTI_line_interrupt
.long TIM8_Break_interrupt
.long TIM8_Update_interrupt
.long TIM8_Trigger_and_Commutation_interrupts
.long TIM8_Capture_Compare_interrupt
.long ADC3_global_interrupt
.long FSMC_global_interrupt
.long SDIO_global_interrupt
.long TIM5_global_interrupt
.long SPI3_global_interrupt
.long UART4_global_interrupt
.long UART5_global_interrupt
.long TIM6_global_interrupt
.long TIM7_global_interrupt
.long DMA2_Channel1_global_interrupt
.long DMA2_Channel2_global_interrupt
.long DMA2_Channel3_global_interrupt
.long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
.weak NMI_interrupt
.weak Hardfault_interrupt
.weak MemManage_interrupt
.weak BusFault_interrupt
.weak UsageFault_interrupt
.weak SWI_interrupt
.weak DebugMonitor_interrupt
.weak PendingSV_interrupt
.weak SysTick_interrupt
.weak Window_watchdog_interrupt
.weak PVD_through_EXTI_Line_detection_interrupt
.weak Tamper_interrupt
.weak RTC_global_interrupt
.weak Flash_global_interrupt
.weak RCC_global_interrupt
.weak EXTI_Line0_interrupt
.weak EXTI_Line1_interrupt
.weak EXTI_Line2_interrupt
.weak EXTI_Line3_interrupt
.weak EXTI_Line4_interrupt
.weak DMA1_Channel1_global_interrupt
.weak DMA1_Channel2_global_interrupt
.weak DMA1_Channel3_global_interrupt
.weak DMA1_Channel4_global_interrupt
.weak DMA1_Channel5_global_interrupt
.weak DMA1_Channel6_global_interrupt
.weak DMA1_Channel7_global_interrupt
.weak ADC1_and_ADC2_global_interrupt
.weak USB_High_Priority_or_CAN_TX_interrupts
.weak USB_Low_Priority_or_CAN_RX0_interrupts
.weak CAN_RX1_interrupt
.weak CAN_SCE_interrupt
.weak EXTI_Line9_5_interrupts
.weak TIM1_Break_interrupt
.weak TIM1_Update_interrupt
.weak TIM1_Trigger_and_Commutation_interrupts
.weak TIM1_Capture_Compare_interrupt
.weak TIM2_global_interrupt
.weak TIM3_global_interrupt
.weak TIM4_global_interrupt
.weak I2C1_event_interrupt
.weak I2C1_error_interrupt
.weak I2C2_event_interrupt
.weak I2C2_error_interrupt
.weak SPI1_global_interrupt
.weak SPI2_global_interrupt
.weak USART1_global_interrupt
.weak USART2_global_interrupt
.weak USART3_global_interrupt
.weak EXTI_Line15_10_interrupts
.weak RTC_alarm_through_EXTI_line_interrupt
.weak USB_wakeup_from_suspend_through_EXTI_line_interrupt
.weak TIM8_Break_interrupt
.weak TIM8_Update_interrupt
.weak TIM8_Trigger_and_Commutation_interrupts
.weak TIM8_Capture_Compare_interrupt
.weak ADC3_global_interrupt
.weak FSMC_global_interrupt
.weak SDIO_global_interrupt
.weak TIM5_global_interrupt
.weak SPI3_global_interrupt
.weak UART4_global_interrupt
.weak UART5_global_interrupt
.weak TIM6_global_interrupt
.weak TIM7_global_interrupt
.weak DMA2_Channel1_global_interrupt
.weak DMA2_Channel2_global_interrupt
.weak DMA2_Channel3_global_interrupt
.weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
.set NMI_interrupt, Startup
.set Hardfault_interrupt, Startup
.set MemManage_interrupt, Startup
.set BusFault_interrupt, Startup
.set UsageFault_interrupt, Startup
.set SWI_interrupt, Startup
.set DebugMonitor_interrupt, Startup
.set PendingSV_interrupt, Startup
.set SysTick_interrupt, Startup
.set Window_watchdog_interrupt, Startup
.set PVD_through_EXTI_Line_detection_interrupt, Startup
.set Tamper_interrupt, Startup
.set RTC_global_interrupt, Startup
.set Flash_global_interrupt, Startup
.set RCC_global_interrupt, Startup
.set EXTI_Line0_interrupt, Startup
.set EXTI_Line1_interrupt, Startup
.set EXTI_Line2_interrupt, Startup
.set EXTI_Line3_interrupt, Startup
.set EXTI_Line4_interrupt, Startup
.set DMA1_Channel1_global_interrupt, Startup
.set DMA1_Channel2_global_interrupt, Startup
.set DMA1_Channel3_global_interrupt, Startup
.set DMA1_Channel4_global_interrupt, Startup
.set DMA1_Channel5_global_interrupt, Startup
.set DMA1_Channel6_global_interrupt, Startup
.set DMA1_Channel7_global_interrupt, Startup
.set ADC1_and_ADC2_global_interrupt, Startup
.set USB_High_Priority_or_CAN_TX_interrupts, Startup
.set USB_Low_Priority_or_CAN_RX0_interrupts, Startup
.set CAN_RX1_interrupt, Startup
.set CAN_SCE_interrupt, Startup
.set EXTI_Line9_5_interrupts, Startup
.set TIM1_Break_interrupt, Startup
.set TIM1_Update_interrupt, Startup
.set TIM1_Trigger_and_Commutation_interrupts, Startup
.set TIM1_Capture_Compare_interrupt, Startup
.set TIM2_global_interrupt, Startup
.set TIM3_global_interrupt, Startup
.set TIM4_global_interrupt, Startup
.set I2C1_event_interrupt, Startup
.set I2C1_error_interrupt, Startup
.set I2C2_event_interrupt, Startup
.set I2C2_error_interrupt, Startup
.set SPI1_global_interrupt, Startup
.set SPI2_global_interrupt, Startup
.set USART1_global_interrupt, Startup
.set USART2_global_interrupt, Startup
.set USART3_global_interrupt, Startup
.set EXTI_Line15_10_interrupts, Startup
.set RTC_alarm_through_EXTI_line_interrupt, Startup
.set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup
.set TIM8_Break_interrupt, Startup
.set TIM8_Update_interrupt, Startup
.set TIM8_Trigger_and_Commutation_interrupts, Startup
.set TIM8_Capture_Compare_interrupt, Startup
.set ADC3_global_interrupt, Startup
.set FSMC_global_interrupt, Startup
.set SDIO_global_interrupt, Startup
.set TIM5_global_interrupt, Startup
.set SPI3_global_interrupt, Startup
.set UART4_global_interrupt, Startup
.set UART5_global_interrupt, Startup
.set TIM6_global_interrupt, Startup
.set TIM7_global_interrupt, Startup
.set DMA2_Channel1_global_interrupt, Startup
.set DMA2_Channel2_global_interrupt, Startup
.set DMA2_Channel3_global_interrupt, Startup
.set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup
.text
end;
end.

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rtl/embedded/arm/stm32f10x_xl.pp Normal file
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{
Register definitions and utility code for STM32F10x - XL density
Created by Jeppe Johansen 2012 - jeppe@j-software.dk
}
unit stm32f10x_xl;
{$goto on}
{$define stm32f10x_xl}
interface
type
TBitvector32 = bitpacked array[0..31] of 0..1;
{$PACKRECORDS 2}
const
PeripheralBase = $40000000;
FSMCBase = $60000000;
APB1Base = PeripheralBase;
APB2Base = PeripheralBase+$10000;
AHBBase = PeripheralBase+$20000;
SCS_BASE = $E000E000;
{ FSMC }
FSMCBank1NOR1 = FSMCBase+$00000000;
FSMCBank1NOR2 = FSMCBase+$04000000;
FSMCBank1NOR3 = FSMCBase+$08000000;
FSMCBank1NOR4 = FSMCBase+$0C000000;
FSMCBank1PSRAM1 = FSMCBase+$00000000;
FSMCBank1PSRAM2 = FSMCBase+$04000000;
FSMCBank1PSRAM3 = FSMCBase+$08000000;
FSMCBank1PSRAM4 = FSMCBase+$0C000000;
FSMCBank2NAND1 = FSMCBase+$10000000;
FSMCBank3NAND2 = FSMCBase+$20000000;
FSMCBank4PCCARD = FSMCBase+$30000000;
type
TTimerRegisters = record
CR1, res1,
CR2, res2,
SMCR, res3,
DIER, res4,
SR, res5,
EGR, res,
CCMR1, res6,
CCMR2, res7,
CCER, res8,
CNT, res9,
PSC, res10,
ARR, res11,
RCR, res12,
CCR1, res13,
CCR2, res14,
CCR3, res15,
CCR4, res16,
BDTR, res17,
DCR, res18,
DMAR, res19: Word;
end;
TRTCRegisters = record
CRH, res1,
CRL, res2,
PRLH, res3,
PRLL, res4,
DIVH, res5,
DIVL, res6,
CNTH, res7,
CNTL, res8,
ALRH, res9,
ALRL, res10: Word;
end;
TIWDGRegisters = record
KR, res1,
PR, res2,
RLR, res3,
SR, res4: word;
end;
TWWDGRegisters = record
CR, res2,
CFR, res3,
SR, res4: word;
end;
TSPIRegisters = record
CR1, res1,
CR2, res2,
SR, res3,
DR, res4,
CRCPR, res5,
RXCRCR, res6,
TXCRCR, res7,
I2SCFGR, res8,
I2SPR, res9: Word;
end;
TUSARTRegisters = record
SR, res1,
DR, res2,
BRR, res3,
CR1, res4,
CR2, res5,
CR3, res6,
GTPR, res7: Word;
end;
TI2CRegisters = record
CR1, res1,
CR2, res2,
OAR1, res3,
OAR2, res4,
DR, res5,
SR1, res6,
SR2, res7,
CCR, res8: word;
TRISE: byte;
end;
TUSBRegisters = record
EPR: array[0..7] of longword;
res: array[0..7] of longword;
CNTR, res1,
ISTR, res2,
FNR, res3: Word;
DADDR: byte; res4: word; res5: byte;
BTABLE: Word;
end;
TUSBMem = packed array[0..511] of byte;
TCANMailbox = record
IR,
DTR,
DLR,
DHR: longword;
end;
TCANRegisters = record
MCR,
MSR,
TSR,
RF0R,
RF1R,
IER,
ESR,
BTR: longword;
res5: array[$020..$17F] of byte;
TX: array[0..2] of TCANMailbox;
RX: array[0..2] of TCANMailbox;
res6: array[$1D0..$1FF] of byte;
FMR,
FM1R,
res9: longword;
FS1R, res10: word;
res11: longword;
FFA1R, res12: word;
res13: longword;
FA1R, res14: word;
res15: array[$220..$23F] of byte;
FOR1,
FOR2: longword;
FB: array[1..13] of array[1..2] of longword;
end;
TBKPRegisters = record
DR: array[1..10] of record data, res: word; end;
RTCCR,
CR,
CSR,
res1,res2: longword;
DR2: array[11..42] of record data, res: word; end;
end;
TPwrRegisters = record
CR, res: word;
CSR: Word;
end;
TDACRegisters = record
CR,
SWTRIGR: longword;
DHR12R1, res2,
DHR12L1, res3,
DHR8R1, res4,
DHR12R2, res5,
DHR12L2, res6,
DHR8R2, res7: word;
DHR12RD,
DHR12LD: longword;
DHR8RD, res8,
DOR1, res9,
DOR2, res10: Word;
end;
TAFIORegisters = record
EVCR,
MAPR: longword;
EXTICR: array[0..3] of longword;
end;
TEXTIRegisters = record
IMR,
EMR,
RTSR,
FTSR,
SWIER,
PR: longword;
end;
TPortRegisters = record
CRL,
CRH,
IDR,
ODR,
BSRR,
BRR,
LCKR: longword;
end;
TADCRegisters = record
SR,
CR1,
CR2,
SMPR1,
SMPR2: longword;
JOFR1, res2,
JOFR2, res3,
JOFR3, res4,
JOFR4, res5,
HTR, res6,
LTR, res7: word;
SQR1,
SQR2,
SQR3,
JSQR: longword;
JDR1, res8,
JDR2, res9,
JDR3, res10,
JDR4, res11: Word;
DR: longword;
end;
TSDIORegisters = record
POWER,
CLKCR,
ARG: longword;
CMD, res3,
RESPCMD, res4: Word;
RESP1,
RESP2,
RESP3,
RESP4,
DTIMER,
DLEN: longword;
DCTRL, res5: word;
DCOUNT,
STA,
ICR,
MASK,
FIFOCNT,
FIFO: longword;
end;
TDMAChannel = record
CCR, res1,
CNDTR, res2: word;
CPAR,
CMAR,
res: longword;
end;
TDMARegisters = record
ISR,
IFCR: longword;
Channel: array[0..7] of TDMAChannel;
end;
TRCCRegisters = record
CR,
CFGR,
CIR,
APB2RSTR,
APB1RSTR,
AHBENR,
APB2ENR,
APB1ENR,
BDCR,
CSR: longword;
end;
TCRCRegisters = record
DR: longword;
IDR: byte; res1: word; res2: byte;
CR: byte;
end;
TFSMCRegisters = record
nothingyet: byte;
end;
TFlashRegisters = record
ACR,
KEYR,
OPTKEYR,
SR,
CR,
AR,
res,
OBR,
WRPR: longword;
end;
TNVICRegisters = record
ISER: array[0..7] of longword;
reserved0: array[0..23] of longword;
ICER: array[0..7] of longword;
reserved1: array[0..23] of longword;
ISPR: array[0..7] of longword;
reserved2: array[0..23] of longword;
ICPR: array[0..7] of longword;
reserved3: array[0..23] of longword;
IABR: array[0..7] of longword;
reserved4: array[0..55] of longword;
IP: array[0..239] of longword;
reserved5: array[0..643] of longword;
STIR: longword;
end;
TSCBRegisters = record
CPUID, {!< CPU ID Base Register }
ICSR, {!< Interrupt Control State Register }
VTOR, {!< Vector Table Offset Register }
AIRCR, {!< Application Interrupt / Reset Control Register }
SCR, {!< System Control Register }
CCR: longword; {!< Configuration Control Register }
SHP: array[0..11] of byte; {!< System Handlers Priority Registers (4-7, 8-11, 12-15) }
SHCSR, {!< System Handler Control and State Register }
CFSR, {!< Configurable Fault Status Register }
HFSR, {!< Hard Fault Status Register }
DFSR, {!< Debug Fault Status Register }
MMFAR, {!< Mem Manage Address Register }
BFAR, {!< Bus Fault Address Register }
AFSR: longword; {!< Auxiliary Fault Status Register }
PFR: array[0..1] of longword; {!< Processor Feature Register }
DFR, {!< Debug Feature Register }
ADR: longword; {!< Auxiliary Feature Register }
MMFR: array[0..3] of longword; {!< Memory Model Feature Register }
ISAR: array[0..4] of longword; {!< ISA Feature Register }
end;
TSysTickRegisters = record
Ctrl,
Load,
Val,
Calib: longword;
end;
{$ALIGN 2}
var
{ Timers }
Timer1: TTimerRegisters absolute (APB2Base+$2C00);
Timer2: TTimerRegisters absolute (APB1Base+$0000);
Timer3: TTimerRegisters absolute (APB1Base+$0400);
Timer4: TTimerRegisters absolute (APB1Base+$0800);
Timer5: TTimerRegisters absolute (APB1Base+$0C00);
Timer6: TTimerRegisters absolute (APB1Base+$1000);
Timer7: TTimerRegisters absolute (APB1Base+$1400);
Timer8: TTimerRegisters absolute (APB2Base+$3400);
{ RTC }
RTC: TRTCRegisters absolute (APB1Base+$2800);
{ WDG }
WWDG: TWWDGRegisters absolute (APB1Base+$2C00);
IWDG: TIWDGRegisters absolute (APB1Base+$3000);
{ SPI }
SPI1: TSPIRegisters absolute (APB2Base+$3000);
SPI2: TSPIRegisters absolute (APB1Base+$3800);
SPI3: TSPIRegisters absolute (APB1Base+$3C00);
{ USART/UART }
USART1: TUSARTRegisters absolute (APB2Base+$3800);
USART2: TUSARTRegisters absolute (APB1Base+$4400);
USART3: TUSARTRegisters absolute (APB1Base+$4800);
UART4: TUSARTRegisters absolute (APB1Base+$4C00);
UART5: TUSARTRegisters absolute (APB1Base+$5000);
{ I2C }
I2C1: TI2CRegisters absolute (APB1Base+$5400);
I2C2: TI2CRegisters absolute (APB1Base+$5800);
{ USB }
USB: TUSBRegisters absolute (APB1Base+$5C00);
USBMem: TUSBMem absolute (APB1Base+$6000);
{ CAN }
CAN: TCANRegisters absolute (APB1Base+$6800);
{ BKP }
BKP: TBKPRegisters absolute (APB1Base+$6C00);
{ PWR }
PWR: TPwrRegisters absolute (APB1Base+$7000);
{ DAC }
DAC: TDACRegisters absolute (APB1Base+$7400);
{ GPIO }
AFIO: TAFIORegisters absolute (APB2Base+$0);
EXTI: TEXTIRegisters absolute (APB2Base+$0400);
PortA: TPortRegisters absolute (APB2Base+$0800);
PortB: TPortRegisters absolute (APB2Base+$0C00);
PortC: TPortRegisters absolute (APB2Base+$1000);
PortD: TPortRegisters absolute (APB2Base+$1400);
PortE: TPortRegisters absolute (APB2Base+$1800);
PortF: TPortRegisters absolute (APB2Base+$1C00);
PortG: TPortRegisters absolute (APB2Base+$2000);
{ ADC }
ADC1: TADCRegisters absolute (APB2Base+$2400);
ADC2: TADCRegisters absolute (APB2Base+$2800);
ADC3: TADCRegisters absolute (APB2Base+$3C00);
{ SDIO }
SDIO: TSDIORegisters absolute (APB2Base+$8000);
{ DMA }
DMA1: TDMARegisters absolute (AHBBase+$0000);
DMA2: TDMARegisters absolute (AHBBase+$0400);
{ RCC }
RCC: TRCCRegisters absolute (AHBBase+$1000);
{ Flash }
Flash: TFlashRegisters absolute (AHBBase+$2000);
{ CRC }
CRC: TCRCRegisters absolute (AHBBase+$3000);
{ SCB }
SCB: TSCBRegisters absolute (SCS_BASE+$0D00);
{ SysTick }
SysTick: TSysTickRegisters absolute (SCS_BASE+$0010);
{ NVIC }
NVIC: TNVICRegisters absolute (SCS_BASE+$0100);
implementation
procedure NMI_interrupt; external name 'NMI_interrupt';
procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
procedure MemManage_interrupt; external name 'MemManage_interrupt';
procedure BusFault_interrupt; external name 'BusFault_interrupt';
procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
procedure SWI_interrupt; external name 'SWI_interrupt';
procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
procedure SysTick_interrupt; external name 'SysTick_interrupt';
procedure Window_watchdog_interrupt; external name 'Window_watchdog_interrupt';
procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
procedure Tamper_interrupt; external name 'Tamper_interrupt';
procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
procedure USB_High_Priority_or_CAN_TX_interrupts; external name 'USB_High_Priority_or_CAN_TX_interrupts';
procedure USB_Low_Priority_or_CAN_RX0_interrupts; external name 'USB_Low_Priority_or_CAN_RX0_interrupts';
procedure CAN_RX1_interrupt; external name 'CAN_RX1_interrupt';
procedure CAN_SCE_interrupt; external name 'CAN_SCE_interrupt';
procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
procedure TIM1_Break_TIM9_global_interrupt; external name 'TIM1_Break_TIM9_global_interrupt';
procedure TIM1_Update_TIM10_global_interrupt; external name 'TIM1_Update_TIM10_global_interrupt';
procedure TIM1_Trigger_and_Commutation_TIM11_global_interrupts; external name 'TIM1_Trigger_and_Commutation_TIM11_global_interrupts';
procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
procedure USB_wakeup_from_suspend_through_EXTI_line_interrupt; external name 'USB_wakeup_from_suspend_through_EXTI_line_interrupt';
procedure TIM8_Break_TIM12_global_interrupt; external name 'TIM8_Break_TIM12_global_interrupt';
procedure TIM8_Update_TIM13_global_interrupt; external name 'TIM8_Update_TIM13_global_interrupt';
procedure TIM8_Trigger_and_Commutation_TIM14_global_interrupts; external name 'TIM8_Trigger_and_Commutation_TIM14_global_interrupts';
procedure TIM8_Capture_Compare_interrupt; external name 'TIM8_Capture_Compare_interrupt';
procedure ADC3_global_interrupt; external name 'ADC3_global_interrupt';
procedure FSMC_global_interrupt; external name 'FSMC_global_interrupt';
procedure SDIO_global_interrupt; external name 'SDIO_global_interrupt';
procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
procedure DMA2_Channel4_and_DMA2_Channel5_global_interrupts; external name 'DMA2_Channel4_and_DMA2_Channel5_global_interrupts';
{$i cortexm3_start.inc}
procedure Vectors; assembler; nostackframe;
label interrupt_vectors;
asm
.section ".init.interrupt_vectors"
interrupt_vectors:
.long _stack_top
.long Startup
.long NMI_interrupt
.long Hardfault_interrupt
.long MemManage_interrupt
.long BusFault_interrupt
.long UsageFault_interrupt
.long 0
.long 0
.long 0
.long 0
.long SWI_interrupt
.long DebugMonitor_interrupt
.long 0
.long PendingSV_interrupt
.long SysTick_interrupt
.long Window_watchdog_interrupt
.long PVD_through_EXTI_Line_detection_interrupt
.long Tamper_interrupt
.long RTC_global_interrupt
.long Flash_global_interrupt
.long RCC_global_interrupt
.long EXTI_Line0_interrupt
.long EXTI_Line1_interrupt
.long EXTI_Line2_interrupt
.long EXTI_Line3_interrupt
.long EXTI_Line4_interrupt
.long DMA1_Channel1_global_interrupt
.long DMA1_Channel2_global_interrupt
.long DMA1_Channel3_global_interrupt
.long DMA1_Channel4_global_interrupt
.long DMA1_Channel5_global_interrupt
.long DMA1_Channel6_global_interrupt
.long DMA1_Channel7_global_interrupt
.long ADC1_and_ADC2_global_interrupt
.long USB_High_Priority_or_CAN_TX_interrupts
.long USB_Low_Priority_or_CAN_RX0_interrupts
.long CAN_RX1_interrupt
.long CAN_SCE_interrupt
.long EXTI_Line9_5_interrupts
.long TIM1_Break_TIM9_global_interrupt
.long TIM1_Update_TIM10_global_interrupt
.long TIM1_Trigger_and_Commutation_TIM11_global_interrupts
.long TIM1_Capture_Compare_interrupt
.long TIM2_global_interrupt
.long TIM3_global_interrupt
.long TIM4_global_interrupt
.long I2C1_event_interrupt
.long I2C1_error_interrupt
.long I2C2_event_interrupt
.long I2C2_error_interrupt
.long SPI1_global_interrupt
.long SPI2_global_interrupt
.long USART1_global_interrupt
.long USART2_global_interrupt
.long USART3_global_interrupt
.long EXTI_Line15_10_interrupts
.long RTC_alarm_through_EXTI_line_interrupt
.long USB_wakeup_from_suspend_through_EXTI_line_interrupt
.long TIM8_Break_TIM12_global_interrupt
.long TIM8_Update_TIM13_global_interrupt
.long TIM8_Trigger_and_Commutation_TIM14_global_interrupts
.long TIM8_Capture_Compare_interrupt
.long ADC3_global_interrupt
.long FSMC_global_interrupt
.long SDIO_global_interrupt
.long TIM5_global_interrupt
.long SPI3_global_interrupt
.long UART4_global_interrupt
.long UART5_global_interrupt
.long TIM6_global_interrupt
.long TIM7_global_interrupt
.long DMA2_Channel1_global_interrupt
.long DMA2_Channel2_global_interrupt
.long DMA2_Channel3_global_interrupt
.long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
.weak NMI_interrupt
.weak Hardfault_interrupt
.weak MemManage_interrupt
.weak BusFault_interrupt
.weak UsageFault_interrupt
.weak SWI_interrupt
.weak DebugMonitor_interrupt
.weak PendingSV_interrupt
.weak SysTick_interrupt
.weak Window_watchdog_interrupt
.weak PVD_through_EXTI_Line_detection_interrupt
.weak Tamper_interrupt
.weak RTC_global_interrupt
.weak Flash_global_interrupt
.weak RCC_global_interrupt
.weak EXTI_Line0_interrupt
.weak EXTI_Line1_interrupt
.weak EXTI_Line2_interrupt
.weak EXTI_Line3_interrupt
.weak EXTI_Line4_interrupt
.weak DMA1_Channel1_global_interrupt
.weak DMA1_Channel2_global_interrupt
.weak DMA1_Channel3_global_interrupt
.weak DMA1_Channel4_global_interrupt
.weak DMA1_Channel5_global_interrupt
.weak DMA1_Channel6_global_interrupt
.weak DMA1_Channel7_global_interrupt
.weak ADC1_and_ADC2_global_interrupt
.weak USB_High_Priority_or_CAN_TX_interrupts
.weak USB_Low_Priority_or_CAN_RX0_interrupts
.weak CAN_RX1_interrupt
.weak CAN_SCE_interrupt
.weak EXTI_Line9_5_interrupts
.weak TIM1_Break_TIM9_global_interrupt
.weak TIM1_Update_TIM10_global_interrupt
.weak TIM1_Trigger_and_Commutation_TIM11_global_interrupts
.weak TIM1_Capture_Compare_interrupt
.weak TIM2_global_interrupt
.weak TIM3_global_interrupt
.weak TIM4_global_interrupt
.weak I2C1_event_interrupt
.weak I2C1_error_interrupt
.weak I2C2_event_interrupt
.weak I2C2_error_interrupt
.weak SPI1_global_interrupt
.weak SPI2_global_interrupt
.weak USART1_global_interrupt
.weak USART2_global_interrupt
.weak USART3_global_interrupt
.weak EXTI_Line15_10_interrupts
.weak RTC_alarm_through_EXTI_line_interrupt
.weak USB_wakeup_from_suspend_through_EXTI_line_interrupt
.weak TIM8_Break_TIM12_global_interrupt
.weak TIM8_Update_TIM13_global_interrupt
.weak TIM8_Trigger_and_Commutation_TIM14_global_interrupts
.weak TIM8_Capture_Compare_interrupt
.weak ADC3_global_interrupt
.weak FSMC_global_interrupt
.weak SDIO_global_interrupt
.weak TIM5_global_interrupt
.weak SPI3_global_interrupt
.weak UART4_global_interrupt
.weak UART5_global_interrupt
.weak TIM6_global_interrupt
.weak TIM7_global_interrupt
.weak DMA2_Channel1_global_interrupt
.weak DMA2_Channel2_global_interrupt
.weak DMA2_Channel3_global_interrupt
.weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
.set NMI_interrupt, Startup
.set Hardfault_interrupt, Startup
.set MemManage_interrupt, Startup
.set BusFault_interrupt, Startup
.set UsageFault_interrupt, Startup
.set SWI_interrupt, Startup
.set DebugMonitor_interrupt, Startup
.set PendingSV_interrupt, Startup
.set SysTick_interrupt, Startup
.set Window_watchdog_interrupt, Startup
.set PVD_through_EXTI_Line_detection_interrupt, Startup
.set Tamper_interrupt, Startup
.set RTC_global_interrupt, Startup
.set Flash_global_interrupt, Startup
.set RCC_global_interrupt, Startup
.set EXTI_Line0_interrupt, Startup
.set EXTI_Line1_interrupt, Startup
.set EXTI_Line2_interrupt, Startup
.set EXTI_Line3_interrupt, Startup
.set EXTI_Line4_interrupt, Startup
.set DMA1_Channel1_global_interrupt, Startup
.set DMA1_Channel2_global_interrupt, Startup
.set DMA1_Channel3_global_interrupt, Startup
.set DMA1_Channel4_global_interrupt, Startup
.set DMA1_Channel5_global_interrupt, Startup
.set DMA1_Channel6_global_interrupt, Startup
.set DMA1_Channel7_global_interrupt, Startup
.set ADC1_and_ADC2_global_interrupt, Startup
.set USB_High_Priority_or_CAN_TX_interrupts, Startup
.set USB_Low_Priority_or_CAN_RX0_interrupts, Startup
.set CAN_RX1_interrupt, Startup
.set CAN_SCE_interrupt, Startup
.set EXTI_Line9_5_interrupts, Startup
.set TIM1_Break_TIM9_global_interrupt, Startup
.set TIM1_Update_TIM10_global_interrupt, Startup
.set TIM1_Trigger_and_Commutation_TIM11_global_interrupts, Startup
.set TIM1_Capture_Compare_interrupt, Startup
.set TIM2_global_interrupt, Startup
.set TIM3_global_interrupt, Startup
.set TIM4_global_interrupt, Startup
.set I2C1_event_interrupt, Startup
.set I2C1_error_interrupt, Startup
.set I2C2_event_interrupt, Startup
.set I2C2_error_interrupt, Startup
.set SPI1_global_interrupt, Startup
.set SPI2_global_interrupt, Startup
.set USART1_global_interrupt, Startup
.set USART2_global_interrupt, Startup
.set USART3_global_interrupt, Startup
.set EXTI_Line15_10_interrupts, Startup
.set RTC_alarm_through_EXTI_line_interrupt, Startup
.set USB_wakeup_from_suspend_through_EXTI_line_interrupt, Startup
.set TIM8_Break_TIM12_global_interrupt, Startup
.set TIM8_Update_TIM13_global_interrupt, Startup
.set TIM8_Trigger_and_Commutation_TIM14_global_interrupts, Startup
.set TIM8_Capture_Compare_interrupt, Startup
.set ADC3_global_interrupt, Startup
.set FSMC_global_interrupt, Startup
.set SDIO_global_interrupt, Startup
.set TIM5_global_interrupt, Startup
.set SPI3_global_interrupt, Startup
.set UART4_global_interrupt, Startup
.set UART5_global_interrupt, Startup
.set TIM6_global_interrupt, Startup
.set TIM7_global_interrupt, Startup
.set DMA2_Channel1_global_interrupt, Startup
.set DMA2_Channel2_global_interrupt, Startup
.set DMA2_Channel3_global_interrupt, Startup
.set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, Startup
.text
end;
end.