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Don't reuse registers on ARM 64 bits shift
git-svn-id: trunk@26669 -
This commit is contained in:
masta
parent
cdc5e9a73a
commit
80d2ee8ad0
@ -438,7 +438,8 @@ implementation
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function tarmshlshrnode.first_shlshr64bitint: tnode;
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begin
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if GenerateThumbCode or GenerateThumb2Code then
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if GenerateThumbCode or GenerateThumb2Code then//or
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// (right.nodetype <> ordconstn) then
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result:=inherited
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else
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result := nil;
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@ -446,70 +447,81 @@ implementation
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procedure tarmshlshrnode.second_64bit;
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var
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hreg64hi,hreg64lo,shiftreg:Tregister;
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v : TConstExprInt;
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l1,l2,l3:Tasmlabel;
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so: tshifterop;
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lreg, resreg: TRegister64;
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procedure emit_instr(p: tai);
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begin
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current_asmdata.CurrAsmList.concat(p);
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end;
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{Reg1 gets shifted and moved into reg2, and is set to zero afterwards}
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procedure shift_more_than_32(reg1, reg2: TRegister; shiftval: Byte ; sm: TShiftMode);
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begin
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shifterop_reset(so); so.shiftimm:=shiftval - 32; so.shiftmode:=sm;
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so));
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emit_instr(taicpu.op_reg_const(A_MOV, reg1, 0));
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end;
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procedure shift_less_than_32(reg1, reg2: TRegister; shiftval: Byte; shiftright: boolean);
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begin
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shifterop_reset(so); so.shiftimm:=shiftval;
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if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
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if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
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so.shiftimm:=32-shiftval;
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emit_instr(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg1, reg1, reg2, so));
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if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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so.shiftimm:=shiftval;
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so));
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end;
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procedure shift_by_variable(reg1, reg2, shiftval: TRegister; shiftright: boolean);
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var
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shiftval2:TRegister;
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{This code is build like it gets called with sm=SM_LSR all the time, for SM_LSL dst* and src* have to be reversed}
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procedure shift_less_than_32(srchi, srclo, dsthi, dstlo: TRegister; shiftval: Byte; sm: TShiftMode);
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begin
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shifterop_reset(so);
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so.shiftimm:=shiftval;
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so.shiftmode:=sm;
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, dstlo, srclo, so));
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, dsthi, srchi, so));
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if sm = SM_LSR then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
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so.shiftimm:=32-shiftval;
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emit_instr(taicpu.op_reg_reg_reg_shifterop(A_ORR, dstlo, dstlo, srchi, so));
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end;
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{This code is build like it gets called with sm=SM_LSR all the time, for SM_LSL dst* and src* have to be reversed
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This will generate
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mov shiftval1, shiftval
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cmp shiftval1, #64
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movcs shiftval1, #64
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rsb shiftval2, shiftval1, #32
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mov dstlo, srclo, lsr shiftval1
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mov dsthi, srchi, lsr shiftval1
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orr dstlo, srchi, lsl shiftval2
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subs shiftval2, shiftval1, #32
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movpl dstlo, srchi, lsr shiftval2
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}
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procedure shift_by_variable(srchi, srclo, dsthi, dstlo, shiftval: TRegister; sm: TShiftMode);
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var
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shiftval1,shiftval2:TRegister;
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begin
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shifterop_reset(so);
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shiftval1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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shiftval2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList, OS_INT, OS_INT, shiftval, shiftval1);
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{The ARM barrel shifter only considers the lower 8 bits of a register for the shift}
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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{Do we shift more than 32 bits?}
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emit_instr(setoppostfix(taicpu.op_reg_reg_const(A_RSB, shiftval2, shiftval, 32), PF_S));
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{This part cares for 32 bits and more}
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emit_instr(setcondition(taicpu.op_reg_reg_const(A_SUB, shiftval2, shiftval, 32), C_MI));
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if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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so.rs:=shiftval2;
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emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg1, so), C_MI));
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{Less than 32 bits}
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so.rs:=shiftval;
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emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, reg2, reg2, so), C_PL));
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if shiftright then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
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so.rs:=shiftval2;
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emit_instr(setcondition(taicpu.op_reg_reg_reg_shifterop(A_ORR, reg2, reg2, reg1, so), C_PL));
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emit_instr(taicpu.op_reg_const(A_CMP, shiftval1, 64));
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emit_instr(setcondition(taicpu.op_reg_const(A_MOV, shiftval1, 64), C_CS));
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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{Final adjustments}
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if shiftright then so.shiftmode:=SM_LSR else so.shiftmode:=SM_LSL;
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so.rs:=shiftval;
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, reg1, reg1, so));
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{Calculate how much the upper register needs to be shifted left}
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emit_instr(taicpu.op_reg_reg_const(A_RSB, shiftval2, shiftval1, 32));
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so.shiftmode:=sm;
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so.rs:=shiftval1;
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{Shift and zerofill the hi+lo register}
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, dstlo, srclo, so));
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, dsthi, srchi, so));
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{Fold in the lower 32-shiftval bits}
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if sm = SM_LSR then so.shiftmode:=SM_LSL else so.shiftmode:=SM_LSR;
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so.rs:=shiftval2;
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emit_instr(taicpu.op_reg_reg_reg_shifterop(A_ORR, dstlo, dstlo, srchi, so));
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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emit_instr(setoppostfix(taicpu.op_reg_reg_const(A_SUB, shiftval2, shiftval1, 32), PF_S));
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so.shiftmode:=sm;
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emit_instr(setcondition(taicpu.op_reg_reg_shifterop(A_MOV, dstlo, srchi, so), C_PL));
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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end;
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begin
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@ -520,13 +532,18 @@ implementation
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end;
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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{ load left operator in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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location.register64.reghi:=hreg64hi;
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location.register64.reglo:=hreg64lo;
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if not(left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
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(left.location.size<>OS_64) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,true);
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lreg := left.location.register64;
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resreg := location.register64;
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shifterop_reset(so);
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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@ -538,8 +555,8 @@ implementation
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begin
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{Shift left by one by 2 simple 32bit additions}
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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emit_instr(setoppostfix(taicpu.op_reg_reg_reg(A_ADD, hreg64lo, hreg64lo, hreg64lo), PF_S));
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emit_instr(taicpu.op_reg_reg_reg(A_ADC, hreg64hi, hreg64hi, hreg64hi));
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emit_instr(setoppostfix(taicpu.op_reg_reg_reg(A_ADD, resreg.reglo, lreg.reglo, lreg.reglo), PF_S));
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emit_instr(taicpu.op_reg_reg_reg(A_ADC, resreg.reghi, lreg.reghi, lreg.reghi));
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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end
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else
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@ -547,42 +564,41 @@ implementation
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{Shift right by first shifting hi by one and then using RRX (rotate right extended), which rotates through the carry}
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shifterop_reset(so); so.shiftmode:=SM_LSR; so.shiftimm:=1;
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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emit_instr(setoppostfix(taicpu.op_reg_reg_shifterop(A_MOV, hreg64hi, hreg64hi, so), PF_S));
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emit_instr(setoppostfix(taicpu.op_reg_reg_shifterop(A_MOV, resreg.reghi, lreg.reghi, so), PF_S));
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so.shiftmode:=SM_RRX; so.shiftimm:=0; {RRX does NOT have a shift amount}
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, hreg64lo, hreg64lo, so));
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emit_instr(taicpu.op_reg_reg_shifterop(A_MOV, resreg.reglo, lreg.reglo, so));
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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end
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{A 32bit shift just replaces a register and clears the other}
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else if v = 32 then
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{Clear one register and use the cg to generate a normal 32-bit shift}
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else if v >= 32 then
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if nodetype=shln then
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begin
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if nodetype=shln then
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emit_instr(taicpu.op_reg_const(A_MOV, hreg64hi, 0))
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else
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emit_instr(taicpu.op_reg_const(A_MOV, hreg64lo, 0));
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location.register64.reghi:=hreg64lo;
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location.register64.reglo:=hreg64hi;
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emit_instr(taicpu.op_reg_const(A_MOV, resreg.reglo, 0));
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,v.uvalue-32,lreg.reglo,resreg.reghi);
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end
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{Shift LESS than 32}
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else
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begin
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emit_instr(taicpu.op_reg_const(A_MOV, resreg.reghi, 0));
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,v.uvalue-32,lreg.reghi,resreg.reglo);
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end
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{Shift LESS than 32, thats the tricky one}
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else if (v < 32) and (v > 1) then
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if nodetype=shln then
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shift_less_than_32(hreg64hi, hreg64lo, v.uvalue, false)
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shift_less_than_32(lreg.reglo, lreg.reghi, resreg.reglo, resreg.reghi, v.uvalue, SM_LSL)
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else
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shift_less_than_32(hreg64lo, hreg64hi, v.uvalue, true)
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{More than 32}
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else if v > 32 then
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if nodetype=shln then
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shift_more_than_32(hreg64lo, hreg64hi, v.uvalue, SM_LSL)
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else
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shift_more_than_32(hreg64hi, hreg64lo, v.uvalue, SM_LSR);
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shift_less_than_32(lreg.reghi, lreg.reglo, resreg.reghi, resreg.reglo, v.uvalue, SM_LSR);
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end
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else
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begin
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{ force right operators in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,resultdef,false);
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{ force right operator into a register }
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if not(right.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
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(right.location.size<>OS_32) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,u32inttype,true);
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if nodetype = shln then
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shift_by_variable(hreg64lo,hreg64hi,right.location.register, false)
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shift_by_variable(lreg.reglo, lreg.reghi, resreg.reglo, resreg.reghi, right.location.register, SM_LSL)
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else
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shift_by_variable(hreg64hi,hreg64lo,right.location.register, true);
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shift_by_variable(lreg.reghi, lreg.reglo, resreg.reghi, resreg.reglo, right.location.register, SM_LSR);
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end;
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end;
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