* x86 asm reader: Don't copy operand size to instruction size for MOVSS and VMOVSS, because it is different for source and destination. Fixes breakage caused by fixing memory size of those instructions (Mantis #29954 and Mantis #29957).

+ Tests are extended to check that both OPR_LOCAL and OPR_REF memory operands compile without warnings as source and destination, in both Intel and AT&T syntax.

git-svn-id: trunk@35081 -

compiler/x86/rax86.pas

@@ -889,6 +889,8 @@ begin
                   end;
               end;
             end;
+          A_MOVSS,
+          A_VMOVSS,
           A_MOVD : { movd is a move from a mmx register to a
                      32 bit register or memory, so no opsize is correct here PM }
             exit;

tests/webtbs/tw29954.pp

@@ -2,12 +2,46 @@
 { %cpu=i386,x86_64 }
 { %opt=-Sew -vw }
 {$mode objfpc}
-{$asmmode intel}
 { The test checks that MOVSS instruction assembles without warning.
   Running it could be a nice bonus, but it turns out that we have no portable
   way to detect SSE4.1 support (for DPPS), so disabled for now. }
 uses cpu;
 
+{$asmmode att}
+procedure test1; assembler;
+var
+  s: single;
+asm
+   movss  s, %xmm6
+   movss  %xmm6, s
+{$ifdef cpui386}
+   movss  (%eax, %edx), %xmm7
+   movss  %xmm7, (%eax, %edx)
+{$endif}
+{$ifdef cpux86_64}
+   movss  (%rax, %rdx), %xmm7
+   movss  %xmm7, (%rax, %rdx)
+{$endif}
+end;
+
+{$asmmode intel}
+procedure test2; assembler;
+var
+  s: single;
+asm
+  movss  [s], xmm6
+  movss  xmm6, [s]
+{$ifdef cpui386}
+  movss  [eax+edx], xmm7
+  movss  xmm7, [eax+edx]
+{$endif}
+{$ifdef cpux86_64}
+  movss  [rax+rdx], xmm7
+  movss  xmm7, [rax+rdx]
+{$endif}
+end;
+
+
 type
    TVector4 = packed record
      X, Y, Z, W: Single;

tests/webtbs/tw29957.pp

@@ -1,8 +1,43 @@
 { %cpu=i386,x86_64 }
+{ %opt=-Sew -vw }
 {$mode objfpc}
-{$asmmode intel}
 uses cpu;
 
+{$asmmode att}
+procedure test1; assembler;
+var
+  s: single;
+asm
+   vmovss  s, %xmm6
+   vmovss  %xmm6, s
+{$ifdef cpui386}
+   vmovss  (%eax, %edx), %xmm7
+   vmovss  %xmm7, (%eax, %edx)
+{$endif}
+{$ifdef cpux86_64}
+   vmovss  (%rax, %rdx), %xmm7
+   vmovss  %xmm7, (%rax, %rdx)
+{$endif}
+end;
+
+{$asmmode intel}
+procedure test2; assembler;
+var
+  s: single;
+asm
+  vmovss  [s], xmm6
+  vmovss  xmm6, [s]
+{$ifdef cpui386}
+  vmovss  [eax+edx], xmm7
+  vmovss  xmm7, [eax+edx]
+{$endif}
+{$ifdef cpux86_64}
+  vmovss  [rax+rdx], xmm7
+  vmovss  xmm7, [rax+rdx]
+{$endif}
+end;
+
+
 type
    TVector4 = packed record
      X, Y, Z, W: Single;