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* x86: New AND(NOT X)->BTR peephole optimisation
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
827fe2bd83
commit
8220221866
@ -13531,34 +13531,90 @@ unit aoptx86;
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function TX86AsmOptimizer.PostPeepholeOptAnd(var p : tai) : boolean;
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var
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hp1: tai;
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Value: TCGInt;
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begin
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{ Detect:
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andw x, %ax (0 <= x < $8000)
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...
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movzwl %ax,%eax
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Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
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}
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Result := False; if MatchOpType(taicpu(p), top_const, top_reg) and
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(taicpu(p).oper[1]^.reg = NR_AX) and { This is also enough to determine that opsize = S_W }
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((taicpu(p).oper[0]^.val and $7FFF) = taicpu(p).oper[0]^.val) and
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GetNextInstructionUsingReg(p, hp1, NR_EAX) and
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MatchInstruction(hp1, A_MOVZX, [S_WL]) and
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MatchOperand(taicpu(hp1).oper[0]^, NR_AX) and
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MatchOperand(taicpu(hp1).oper[1]^, NR_EAX) then
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Result := False;
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if MatchOpType(taicpu(p), top_const, top_reg) then
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begin
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DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via AndMovz2AndCwtl)', hp1);
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taicpu(hp1).opcode := A_CWDE;
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taicpu(hp1).clearop(0);
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taicpu(hp1).clearop(1);
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taicpu(hp1).ops := 0;
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{ Detect:
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andw x, %ax (0 <= x < $8000)
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...
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movzwl %ax,%eax
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{ A change was made, but not with p, so move forward 1 }
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p := tai(p.Next);
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Result := True;
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Change movzwl %ax,%eax to cwtl (shorter encoding for movswl %ax,%eax)
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}
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if (taicpu(p).oper[1]^.reg = NR_AX) and { This is also enough to determine that opsize = S_W }
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((taicpu(p).oper[0]^.val and $7FFF) = taicpu(p).oper[0]^.val) and
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GetNextInstructionUsingReg(p, hp1, NR_EAX) and
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MatchInstruction(hp1, A_MOVZX, [S_WL]) and
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MatchOperand(taicpu(hp1).oper[0]^, NR_AX) and
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MatchOperand(taicpu(hp1).oper[1]^, NR_EAX) then
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begin
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DebugMsg(SPeepholeOptimization + 'Converted movzwl %ax,%eax to cwtl (via AndMovz2AndCwtl)', hp1);
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taicpu(hp1).opcode := A_CWDE;
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taicpu(hp1).clearop(0);
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taicpu(hp1).clearop(1);
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taicpu(hp1).ops := 0;
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{ A change was made, but not with p, so move forward 1 }
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p := tai(p.Next);
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Result := True;
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Exit; { and -> btr won't happen because an opsize of S_W won't be optimised anyway }
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end;
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{ If "not x" is a power of 2 (popcnt = 1), change:
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and $x, %reg/ref
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To:
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btr lb(x), %reg/ref
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}
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if
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{$ifndef x86_64}
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(
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(cs_opt_size in current_settings.optimizerswitches) or
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{ BTR takes more than 1 cycle on earlier processors }
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(current_settings.optimizecputype >= cpu_Pentium2)
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) and
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{$endif not x86_64}
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{ For sizes less than S_L, the byte size is equal or larger with BT,
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so don't bother optimising }
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(taicpu(p).opsize >= S_L) and
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{ "btx $x,mem" is unacceptably slow, but oper[1] being top_reg is already checked }
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(
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{ If the value can bit into an 8-bit signed integer, a smaller
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instruction can be encded with OR, so don't optimise if it falls
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within this range }
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(taicpu(p).oper[0]^.val < -128) or
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(taicpu(p).oper[0]^.val >= 127)
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) and
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(
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{ Make sure a TEST doesn't follow that plays with the register }
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not GetNextInstruction(p, hp1) or
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not MatchInstruction(hp1, A_TEST, A_CMP, [taicpu(p).opsize]) or
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not MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[1]^.reg)
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) then
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begin
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{$push}{$R-}{$Q-}
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{ Value is a sign-extended 32-bit integer - just correct it
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if it's represented as an unsigned value }
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Value := not taicpu(p).oper[0]^.val;
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{$pop}
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{$ifdef x86_64}
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if taicpu(p).opsize = S_L then
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{$endif x86_64}
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Value := Value and $FFFFFFFF;
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if (PopCnt(QWord(Value)) = 1) then
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begin
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DebugMsg(SPeepholeOptimization + 'Changed AND (not $0x' + hexstr(taicpu(p).oper[0]^.val, 2) + ') to BTR ' + debug_tostr(BsrQWord(Value)) + ' to shrink instruction size (And2Btr)', p);
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taicpu(p).opcode := A_BTR;
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taicpu(p).oper[0]^.val := BsrQWord(Value); { Essentially the base 2 logarithm }
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Result := True;
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Exit;
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end;
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end;
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end;
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end;
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@ -14075,10 +14131,19 @@ unit aoptx86;
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jnc / setnc / cmovnc (or jc / setc / cmovnc)
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}
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if (taicpu(p).opcode = A_TEST) and
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{$ifdef i8086}
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(current_settings.optimizecputype >= cpu_386) and
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{$endif i8086}
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MatchOpType(taicpu(p), top_const, top_reg) and { "btx $x,mem" is unacceptably slow }
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(CPUX86_HAS_BTX in cpu_capabilities[current_settings.optimizecputype]) and
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(taicpu(p).oper[0]^.typ = top_const) and
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(
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(cs_opt_size in current_settings.optimizerswitches) or
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(
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(taicpu(p).oper[1]^.typ = top_reg) and
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(CPUX86_HAS_FAST_BTX in cpu_capabilities[current_settings.optimizecputype])
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) or
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(
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(taicpu(p).oper[1]^.typ <> top_reg) and
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(CPUX86_HAS_FAST_BT_MEM in cpu_capabilities[current_settings.optimizecputype])
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)
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) and
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(PopCnt(QWord(taicpu(p).oper[0]^.val)) = 1) and
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{ For sizes less than S_L, the byte size is equal or larger with BT,
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so don't bother optimising }
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