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https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-09-08 09:59:12 +02:00
+ memory references are now replaced by register reads in "regular"
instructions (e.g. "addl ref1,%eax" will be replaced by "addl %ebx,%eax"
if %ebx contains ref1). Previously only complete load sequences were
optimized away, but not such small accesses in other instructions than
mov/movzx/movsx
This commit is contained in:
Jonas Maebe
parent
97c1152c6d
commit
82f7cf0957
@ -185,10 +185,7 @@ function isSimpleMemLoc(const ref: treference): boolean;
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begin
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isSimpleMemLoc :=
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(ref.index = R_NO) and
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(not(ref.base in (usableregs+[R_EDI])) or
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(assigned(ref.symbol) and
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(ref.base = R_NO) and
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(ref.index = R_NO)));
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not(ref.base in (usableregs+[R_EDI]));
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end;
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{checks whether the current instruction sequence (starting with p) and the
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@ -1314,6 +1311,48 @@ begin
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(p.opcode = A_IDIV));
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end;
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function memtoreg(const t: Taicpu; const ref: treference): tregister;
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var
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hp: tai;
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p: pTaiprop;
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regcounter: tregister;
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begin
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if not getlastinstruction(t,hp) then
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begin
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memtoreg := R_NO;
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exit;
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end;
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p := pTaiprop(hp.optinfo);
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if isSimpleMemLoc(ref) then
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begin
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for regcounter := R_EAX to R_EDI do
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if (p^.regs[regcounter].typ in [CON_REF,CON_NOREMOVEREF]) and
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(p^.regs[regcounter].nrofmods = 1) and
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((Taicpu(p^.regs[regcounter].startmod).opcode = A_MOV) or
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(Taicpu(p^.regs[regcounter].startmod).opcode = A_MOVZX) or
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(Taicpu(p^.regs[regcounter].startmod).opcode = A_MOVSX)) and
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(taicpu(p^.regs[regcounter].startmod).oper[0].typ = top_ref) and
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refsequal(ref,taicpu(p^.regs[regcounter].startmod).oper[0].ref^) then
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begin
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if ((t.opsize <> S_B) or
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(regcounter <> R_EDI)) and
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sizescompatible(Taicpu(p^.regs[regcounter].startmod).opsize,t.opsize) then
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begin
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case t.opsize of
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S_B,S_BW,S_BL:
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memtoreg := reg32toreg8(regcounter);
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S_W,S_WL:
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memtoreg := reg32toreg16(regcounter);
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S_L:
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memtoreg := regcounter;
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end;
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exit;
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end;
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end;
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end;
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memtoreg := R_NO;
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end;
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procedure DoCSE(AsmL: TAAsmOutput; First, Last: Tai; findPrevSeqs, doSubOpts: boolean);
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{marks the instructions that can be removed by RemoveInstructs. They're not
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removed immediately because sometimes an instruction needs to be checked in
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@ -1594,9 +1633,26 @@ Begin
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pTaiProp(p.optInfo)^.regs[Taicpu(p).oper[0].reg].startMod,hp1);
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end
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else
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if (Taicpu(p).oper[1].typ = top_reg) and
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not regInOp(Taicpu(p).oper[1].reg,Taicpu(p).oper[0]) then
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removePrevNotUsedLoad(p,reg32(Taicpu(p).oper[1].reg),false);
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begin
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if (Taicpu(p).oper[1].typ = top_reg) and
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not regInOp(Taicpu(p).oper[1].reg,Taicpu(p).oper[0]) then
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removePrevNotUsedLoad(p,reg32(Taicpu(p).oper[1].reg),false);
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if doSubOpts and
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(Taicpu(p).opcode <> A_LEA) and
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(Taicpu(p).oper[0].typ = top_ref) then
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begin
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regcounter :=
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memtoreg(taicpu(p),
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Taicpu(p).oper[0].ref^);
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if regcounter <> R_NO then
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begin
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Taicpu(p).loadreg(0,regcounter);
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allocregbetween(asml,reg32(regcounter),
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pTaiprop(p.optinfo)^.regs[reg32(regcounter)].startmod,
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p);
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end;
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end;
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end;
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{ at first, only try optimizations of large blocks, because doing }
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{ doing smaller ones may prevent bigger ones from completing in }
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{ in the next pass }
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@ -1643,6 +1699,52 @@ Begin
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A_STD: If GetLastInstruction(p, hp1) And
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(PTaiProp(hp1.OptInfo)^.DirFlag = F_Set) Then
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PTaiProp(Tai(p).OptInfo)^.CanBeRemoved := True;
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else
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begin
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for cnt := 1 to maxch do
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begin
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case InsProp[taicpu(p).opcode].Ch[cnt] of
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Ch_ROp1:
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if (taicpu(p).oper[0].typ = top_ref) and
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((taicpu(p).opcode < A_F2XM1) or
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((taicpu(p).opcode > A_IN) and
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(taicpu(p).opcode < A_OUT)) or
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(taicpu(p).opcode = A_PUSH) or
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(taicpu(p).opcode = A_SUB) or
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(taicpu(p).opcode = A_TEST) or
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(taicpu(p).opcode = A_XOR))then
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begin
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regcounter :=
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memtoreg(taicpu(p),
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Taicpu(p).oper[0].ref^);
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if regcounter <> R_NO then
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begin
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Taicpu(p).loadreg(0,regcounter);
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allocregbetween(asml,reg32(regcounter),
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pTaiprop(p.optinfo)^.regs[reg32(regcounter)].startmod,
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p);
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end;
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end;
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Ch_ROp2:
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if ((taicpu(p).opcode = A_CMP) or
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(taicpu(p).opcode = A_TEST)) and
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(taicpu(p).oper[1].typ = top_ref) then
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begin
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regcounter :=
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memtoreg(taicpu(p),
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Taicpu(p).oper[1].ref^);
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if regcounter <> R_NO then
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begin
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Taicpu(p).loadreg(1,regcounter);
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allocregbetween(asml,reg32(regcounter),
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pTaiprop(p.optinfo)^.regs[reg32(regcounter)].startmod,
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p);
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end;
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end;
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end;
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end;
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end;
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End
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End;
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End;
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@ -1742,7 +1844,14 @@ End.
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{
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$Log$
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Revision 1.18 2001-09-04 14:01:03 jonas
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Revision 1.19 2001-10-12 13:58:05 jonas
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+ memory references are now replaced by register reads in "regular"
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instructions (e.g. "addl ref1,%eax" will be replaced by "addl %ebx,%eax"
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if %ebx contains ref1). Previously only complete load sequences were
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optimized away, but not such small accesses in other instructions than
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mov/movzx/movsx
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Revision 1.18 2001/09/04 14:01:03 jonas
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* commented out some inactive code in csopt386
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+ small improvement: lea is now handled the same as mov/zx/sx
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@ -191,6 +191,7 @@ function FindRegDealloc(reg: tregister; p: Tai): boolean;
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Function RegsEquivalent(OldReg, NewReg: TRegister; Var RegInfo: TRegInfo; OpAct: TopAction): Boolean;
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Function InstructionsEquivalent(p1, p2: Tai; Var RegInfo: TRegInfo): Boolean;
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function sizescompatible(loadsize,newsize: topsize): boolean;
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Function OpsEqual(const o1,o2:toper): Boolean;
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Function DFAPass1(AsmL: TAAsmOutput; BlockStart: Tai): Tai;
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@ -1164,10 +1165,13 @@ var
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lastRemovedWasDealloc, firstRemovedWasAlloc, first: boolean;
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Begin
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If not(reg in usableregs+[R_EDI,R_ESI]) or
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not(assigned(p1)) Then
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not(assigned(p1)) then
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{ this happens with registers which are loaded implicitely, outside the }
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{ current block (e.g. esi with self) }
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exit;
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{ make sure we allocate it for this instruction }
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if p1 = p2 then
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getnextinstruction(p2,p2);
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lastRemovedWasDealloc := false;
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firstRemovedWasAlloc := false;
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first := true;
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@ -1433,6 +1437,34 @@ Begin {checks whether the two ops are equal}
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End;
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End;
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function sizescompatible(loadsize,newsize: topsize): boolean;
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begin
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case loadsize of
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S_B,S_BW,S_BL:
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sizescompatible := (newsize = loadsize) or (newsize = S_B);
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S_W,S_WL:
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sizescompatible := (newsize = loadsize) or (newsize = S_W);
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else
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sizescompatible := newsize = S_L;
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end;
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end;
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function opscompatible(p1,p2: Taicpu): boolean;
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begin
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case p1.opcode of
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A_MOVZX,A_MOVSX:
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opscompatible :=
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((p2.opcode = p1.opcode) or (p2.opcode = A_MOV)) and
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sizescompatible(p1.opsize,p2.opsize);
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else
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opscompatible :=
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(p1.opcode = p2.opcode) and
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(p1.opsize = p2.opsize);
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end;
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end;
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Function InstructionsEquivalent(p1, p2: Tai; Var RegInfo: TRegInfo): Boolean;
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{$ifdef csdebug}
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var
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@ -1442,7 +1474,7 @@ Begin {checks whether two Taicpu instructions are equal}
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If Assigned(p1) And Assigned(p2) And
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(Tai(p1).typ = ait_instruction) And
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(Tai(p1).typ = ait_instruction) And
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(Taicpu(p1).opcode = Taicpu(p2).opcode) And
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opscompatible(Taicpu(p1),Taicpu(p2)) and
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(Taicpu(p1).oper[0].typ = Taicpu(p2).oper[0].typ) And
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(Taicpu(p1).oper[1].typ = Taicpu(p2).oper[1].typ) And
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(Taicpu(p1).oper[2].typ = Taicpu(p2).oper[2].typ)
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@ -1476,7 +1508,8 @@ Begin {checks whether two Taicpu instructions are equal}
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AddOp2RegInfo(Taicpu(p1).oper[0], RegInfo);
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{the registers from .oper[1] have to be equivalent, but not necessarily equal}
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InstructionsEquivalent :=
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RegsEquivalent(Taicpu(p1).oper[1].reg, Taicpu(p2).oper[1].reg, RegInfo, OpAct_Write);
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RegsEquivalent(reg32(Taicpu(p1).oper[1].reg),
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reg32(Taicpu(p2).oper[1].reg), RegInfo, OpAct_Write);
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End
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{the registers are loaded with values from different memory locations. If
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this was allowed, the instructions "mov -4(esi),eax" and "mov -4(ebp),eax"
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@ -2519,7 +2552,14 @@ End.
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{
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$Log$
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Revision 1.21 2001-09-04 14:01:04 jonas
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Revision 1.22 2001-10-12 13:58:05 jonas
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+ memory references are now replaced by register reads in "regular"
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instructions (e.g. "addl ref1,%eax" will be replaced by "addl %ebx,%eax"
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if %ebx contains ref1). Previously only complete load sequences were
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optimized away, but not such small accesses in other instructions than
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mov/movzx/movsx
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Revision 1.21 2001/09/04 14:01:04 jonas
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* commented out some inactive code in csopt386
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+ small improvement: lea is now handled the same as mov/zx/sx
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