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Added generic WCH32Vx RISC-V processor types using memory size suffixes

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Modified low-level startup code for RISCV32 embedded microcontrollers to
allow user code override of reset handlers for non-power-up reset events
as well as enabling user code override handlers for all 255 possible
interrupt vectors.
Separated out the low-level startup memory init into a callable procedure
to allow users that have caught reset events to init memory again if needed.

Signed-off-by: Interferon <brspm2@pinnaclesimulation.com>
This commit is contained in:
Interferon 2023-06-16 20:55:06 -06:00 committed by florian
parent 5930ffa135
commit 8382c6f586
8 changed files with 1242 additions and 61 deletions
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4
compiler/riscv/agrvgas.pas
View File

@ -233,8 +233,8 @@ unit agrvgas;
const
arch_str: array[boolean,tcputype] of string[10] = (
{$ifdef RISCV32}
('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc'),
('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd')
('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32ec'),
('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32ecfd')
{$endif RISCV32}
{$ifdef RISCV64}
('','rv64imac','rv64ima','rv64im','rv64i'),

24
compiler/riscv32/cpuinfo.pas
View File

@ -40,7 +40,8 @@ Type
cpu_rv32im,
cpu_rv32i,
cpu_rv32e,
cpu_rv32imc
cpu_rv32imc,
cpu_rv32ec
);
tfputype =
@ -81,7 +82,12 @@ Type
ct_ch32v307rc,
ct_ch32v307wc,
ct_ch32V307vc,
ct_esp32c3
ct_esp32c3,
ct_CH32V0x,
ct_CH32Vxxxx6,
ct_CH32Vxxxx8,
ct_CH32VxxxxB,
ct_CH32VxxxxC
);
tcontrollerdatatype = record
@ -133,7 +139,12 @@ Const
(controllertypestr:'CH32V307RC'; controllerunitstr:'CH32V307'; cputype:cpu_rv32imac; fputype:fpu_fd; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
(controllertypestr:'CH32V307WC'; controllerunitstr:'CH32V307'; cputype:cpu_rv32imac; fputype:fpu_fd; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
(controllertypestr:'CH32V307VC'; controllerunitstr:'CH32V307'; cputype:cpu_rv32imac; fputype:fpu_fd; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00010000),
(controllertypestr:'ESP32C3'; controllerunitstr:'ESP32C3'; cputype:cpu_rv32imc; fputype:fpu_none; flashbase:$00000000; flashsize:4*1024*1024; srambase:$20000000; sramsize:400*1024)
(controllertypestr:'ESP32C3'; controllerunitstr:'ESP32C3'; cputype:cpu_rv32imc; fputype:fpu_none; flashbase:$00000000; flashsize:4*1024*1024; srambase:$20000000; sramsize:400*1024),
(controllertypestr:'CH32V0X' ; controllerunitstr:'CH32VxBootstrap'; cputype:cpu_rv32e; fputype:fpu_none; flashbase:$00000000; flashsize:$00004000; srambase:$20000000; sramsize:$00000800; eeprombase:0; eepromsize:0;BootBase:$1FFFF000; BootSize:1920),
(controllertypestr:'CH32VXXXX6' ; controllerunitstr:'CH32VxBootstrap'; cputype:cpu_rv32imac; fputype:fpu_none; flashbase:$00000000; flashsize:$00008000; srambase:$20000000; sramsize:$00002800),
(controllertypestr:'CH32VXXXX8' ; controllerunitstr:'CH32VxBootstrap'; cputype:cpu_rv32imac; fputype:fpu_none; flashbase:$00000000; flashsize:$00010000; srambase:$20000000; sramsize:$00008000),
(controllertypestr:'CH32VXXXXB' ; controllerunitstr:'CH32VxBootstrap'; cputype:cpu_rv32imac; fputype:fpu_none; flashbase:$00000000; flashsize:$00020000; srambase:$20000000; sramsize:$00010000),
(controllertypestr:'CH32VXXXXC' ; controllerunitstr:'CH32VxBootstrap'; cputype:cpu_rv32imac; fputype:fpu_none; flashbase:$00000000; flashsize:$00040000; srambase:$20000000; sramsize:$00020000)
);
{$POP}
@ -156,7 +167,8 @@ Const
'RV32IM',
'RV32I',
'RV32E',
'RV32IMC'
'RV32IMC',
'RV32EC'
);
fputypestr : array[tfputype] of string[8] = (
@ -197,7 +209,9 @@ Const
{ cpu_rv32im } [CPURV_HAS_MUL],
{ cpu_rv32i } [],
{ cpu_rv32e } [CPURV_HAS_16REGISTERS],
{ cpu_rv32imc } [CPURV_HAS_MUL,CPURV_HAS_COMPACT]
{ cpu_rv32imc } [CPURV_HAS_MUL,CPURV_HAS_COMPACT],
{ cpu_rv32ec } [CPURV_HAS_16REGISTERS,CPURV_HAS_COMPACT]
);
Implementation

13
rtl/embedded/Makefile.fpc
View File

@ -223,6 +223,17 @@ endif
endif
ifeq ($(ARCH),riscv32)
CPU_SPECIFIC_COMMON_UNITS=sysutils math classes fgl macpas typinfo types rtlconsts getopts lineinfo
ifeq ($(SUBARCH),rv32ec)
override FPCOPT+=-Cprv32ec
CPU_UNITS=CH32VxBootstrap
CPU_UNITS_DEFINED=1
endif
ifeq ($(SUBARCH),rv32e)
override FPCOPT+=-Cprv32e
CPU_UNITS=CH32VxBootstrap
CPU_UNITS_DEFINED=1
endif
ifeq ($(SUBARCH),rv32imac)
override FPCOPT+=-Cprv32imac
CPU_UNITS=$(FE310G000UNIT) $(FE310G002UNIT) $(GD32VF103XXUNIT)
@ -230,7 +241,7 @@ CPU_UNITS_DEFINED=1
endif
ifeq ($(SUBARCH),rv32i)
override FPCOPT+=-Cprv32i
CPU_UNITS=
CPU_UNITS=CH32VxBootstrap
CPU_UNITS_DEFINED=1
endif
ifeq ($(CPU_UNITS_DEFINED),)

1176
rtl/embedded/riscv32/CH32VxBootstrap.pp Normal file
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File diff suppressed because it is too large Load Diff

9
rtl/embedded/riscv32/fe310g000.pp
View File

@ -249,7 +249,7 @@ var
SPI2 : TSPI_Registers absolute SPI2_BASE;
UART0 : TUART_Registers absolute UART0_BASE;
UART1 : TUART_Registers absolute UART1_BASE;
procedure InitMemAndStart; noreturn;
implementation
procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
@ -342,6 +342,11 @@ procedure DCMI_interrupt; external name 'DCMI_interrupt';
procedure HASH_RNG_interrupt; external name 'HASH_RNG_interrupt';
procedure FPU_interrupt; external name 'FPU_interrupt';
procedure ResetISR; external name 'ResetISR';
procedure HandleArchSpecificReset; noreturn;
begin
InitMemAndStart
end;
{$i riscv32_start.inc}
procedure Vectors; assembler; nostackframe;
@ -350,7 +355,7 @@ asm
.section ".init.interrupt_vectors"
interrupt_vectors:
.long _stack_top
.long Startup
.long HandleArchSpecificReset
.long NonMaskableInt_interrupt
.long 0
.long MemoryManagement_interrupt

9
rtl/embedded/riscv32/fe310g002.pp
View File

@ -252,7 +252,7 @@ var
SPI2 : TSPI_Registers absolute SPI2_BASE;
UART0 : TUART_Registers absolute UART0_BASE;
UART1 : TUART_Registers absolute UART1_BASE;
procedure InitMemAndStart; noreturn;
implementation
procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
@ -345,6 +345,11 @@ procedure DCMI_interrupt; external name 'DCMI_interrupt';
procedure HASH_RNG_interrupt; external name 'HASH_RNG_interrupt';
procedure FPU_interrupt; external name 'FPU_interrupt';
procedure ResetISR; external name 'ResetISR';
procedure HandleArchSpecificReset; noreturn;
begin
InitMemAndStart
end;
{$i riscv32_start.inc}
procedure Vectors; assembler; nostackframe;
@ -353,7 +358,7 @@ asm
.section ".init.interrupt_vectors"
interrupt_vectors:
jal _stack_top
jal Startup
jal HandleArchSpecificReset
jal NonMaskableInt_interrupt
.long 0
.long MemoryManagement_interrupt

9
rtl/embedded/riscv32/gd32vf103xx.pp
View File

@ -499,7 +499,7 @@ var
UART3 : TUSART_Registers absolute UART3_BASE;
UART4 : TUSART_Registers absolute UART4_BASE;
WWDGT : TWWDGT_Registers absolute WWDGT_BASE;
procedure InitMemAndStart; noreturn;
implementation
procedure CLIC_RESERVED_ISR; external name 'CLIC_RESERVED_ISR';
procedure CLIC_SFT_ISR; external name 'CLIC_SFT_ISR';
@ -566,7 +566,12 @@ implementation
procedure CAN1_RX1_ISR; external name 'CAN1_RX1_ISR';
procedure CAN1_EWMC_ISR; external name 'CAN1_EWMC_ISR';
procedure USBFS_ISR; external name 'USBFS_ISR';
procedure ResetISR; external name 'ResetISR';
procedure HandleArchSpecificReset; noreturn;
begin
InitMemAndStart
end;
{$i riscv32_start.inc}
procedure Vectors; assembler; nostackframe;

59
rtl/embedded/riscv32/riscv32_start.inc
View File

@ -9,15 +9,17 @@ var
procedure Pascalmain; external name 'PASCALMAIN';
procedure HaltProc; noreturn; public name'_haltproc';
procedure _haltproc; external Name '_haltproc';
procedure HaltProc; noreturn;
begin
while true do;
end;
procedure Startup;
procedure InitMemAndStart; noreturn;
var
pdest, psrc, pend: PLongWord;
begin
pdest:=@_data;
psrc:=@_etext;
pend:=@_bss_start;
@ -40,11 +42,18 @@ begin
HaltProc;
end;
procedure LowlevelStartup; assembler; nostackframe; [public, alias: '_START'];
asm
.weak ResetISR
.set ResetISR, InitMemAndStart;
.weak _haltproc
.set _haltproc, HaltProc
{ Initialize global Pointer }
.option push
.option norelax
lui gp, %hi(_bss_start+0x800)
addi gp, gp, %lo(_bss_start+0x800)
.option pop
@ -57,49 +66,5 @@ asm
{ Initialise FP to zero }
addi fp, x0, 0
jal x0, Startup
// { Copy Initialized vars}
// lui x10,%hi(_data)
// addi x10,x10,%lo(_data)
// lui x11,%hi(_edata)
// addi x11,x11,%lo(_edata)
// sltu x12,x10,x11
// beq x12,x0,.L2
// lui x12,%hi(_etext)
// addi x12,x12,%lo(_etext)
// addi x10,x10,-1
// addi x12,x12,-1
// .L1:
// addi x10,x10,1
// addi x12,x12,1
// lb x13,0(x10)
// sb x13,0(x12)
// bne x10,x11,.L1
// .L2:
// { Initialize Memory}
// lui x10,%hi(_bss_start)
// addi x10,x10,%lo(_bss_start)
// lui x11,%hi(_bss_end)
// addi x11,x11,%lo(_bss_end)
// sltu x12,x10,x11
// beq x12,x0,.L4
// addi x10,x10,-1
// .L3:
// addi x10,x10,1
// sb x0,0(x10)
// bne x10,x11,.L3
// .L4:
// jal x0,PASCALMAIN
// jal x0,HaltProc
// .L_bss_start:
// .long _bss_start
// .L_bss_end:
// .long _bss_end
// .L_etext:
// .long _etext
// .L_data:
// .long _data
// .L_edata:
// .long _edata
// .text
jal x0, HandleArchSpecificReset
end;