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https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-12-16 05:50:40 +01:00
* merged new changes to avx2 branch (AVX2 vectory-memory support) by Torsten Grundke
git-svn-id: trunk@28527 -
This commit is contained in:
florian
parent
4ef87579eb
commit
8635894de4
@ -1827,9 +1827,13 @@ implementation
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{No register, so memory reference.}
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if (input.typ<>top_ref) then
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internalerror(200409262);
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if ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)<>R_INTREGISTER)) or
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if ((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)=R_MMREGISTER) and (input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) or // vector memory (AVX2)
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((input.ref^.index<>NR_NO) and (getregtype(input.ref^.index)<>R_INTREGISTER) and (getregtype(input.ref^.index)<>R_MMREGISTER)) or
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((input.ref^.base<>NR_NO) and (getregtype(input.ref^.base)<>R_INTREGISTER)) then
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internalerror(200301081);
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internalerror(200301081);
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ir:=input.ref^.index;
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br:=input.ref^.base;
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isub:=getsubreg(ir);
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@ -1849,8 +1853,15 @@ implementation
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{ it's an indirection }
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begin
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{ 16 bit address? }
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if ((ir<>NR_NO) and (isub<>R_SUBADDR)) or
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((br<>NR_NO) and (bsub<>R_SUBADDR)) then
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if ((ir<>NR_NO) and (isub in [R_SUBMMX,R_SUBMMY]) and
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(br<>NR_NO) and (bsub=R_SUBADDR)
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) then
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begin
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// vector memory (AVX2) =>> ignore
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end
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else if ((ir<>NR_NO) and (isub<>R_SUBADDR)) or
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((br<>NR_NO) and (bsub<>R_SUBADDR)) then
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message(asmw_e_16bit_not_supported);
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{$ifdef OPTEA}
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{ make single reg base }
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@ -1893,14 +1904,30 @@ implementation
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end;
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{ index }
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case ir of
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NR_EAX : index:=0;
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NR_ECX : index:=1;
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NR_EDX : index:=2;
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NR_EBX : index:=3;
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NR_NO : index:=4;
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NR_EBP : index:=5;
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NR_ESI : index:=6;
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NR_EDI : index:=7;
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NR_EAX,
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NR_XMM0,
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NR_YMM0: index:=0;
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NR_ECX,
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NR_XMM1,
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NR_YMM1: index:=1;
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NR_EDX,
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NR_XMM2,
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NR_YMM2: index:=2;
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NR_EBX,
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NR_XMM3,
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NR_YMM3: index:=3;
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NR_NO,
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NR_XMM4,
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NR_YMM4: index:=4;
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NR_EBP,
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NR_XMM5,
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NR_YMM5: index:=5;
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NR_ESI,
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NR_XMM6,
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NR_YMM6: index:=6;
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NR_EDI,
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NR_XMM7,
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NR_YMM7: index:=7;
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else
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exit;
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end;
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@ -28,7 +28,8 @@ uses BaseList, Classes;
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type
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TOpType = (otUnknown, otXMMReg, otXMMRM, otXMMRM16, otXMMRM8, otYMMReg, otYMMRM, otEAX, otRAX, otMem32,
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otMem8, otMem16, otMem64, otMem128, otMem256, otREG64, otREG32, otRM32, otRM64, otIMM8);
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otMem8, otMem16, otMem64, otMem128, otMem256, otREG64, otREG32, otRM32, otRM64, otIMM8,
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otXMEM32, otXMEM64, otYMEM32, otYMEM64);
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TOperandListItem = class(TObject)
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private
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@ -58,6 +59,8 @@ type
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end;
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{ TAsmTestGenerator }
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TAsmTestGenerator = class(TObject)
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private
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FReg32Base : TStringList;
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@ -66,10 +69,15 @@ type
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FReg64Index : TStringList;
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FReg6432Base : TStringList;
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FReg6432Index : TStringList;
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FReg32XMMIndex : TStringList;
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FReg32YMMIndex : TStringList;
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FReg64XMMIndex : TStringList;
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FReg64YMMIndex : TStringList;
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Fx64: boolean;
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procedure MemRegBaseIndexCombi(const aPrefix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList);
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procedure VectorMemRegBaseIndexCombi(const aPrefix: String; aSLBaseReg, aSLIndexReg, aRList: TStringList);
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function InternalCalcTestData(const aInst, aOp1, aOp2, aOp3, aOp4: String): TStringList;
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public
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@ -583,6 +591,76 @@ begin
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Item.Values.Add('0');
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end
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else if AnsiSameText(sl_Operand, 'XMEM32') then
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begin
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Item.OpNumber := il_Op;
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Item.OpTyp := otXMEM32;
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Item.OpActive := true;
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if UsePrefix then sl_Prefix := 'oword ';
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if x64 then
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begin
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VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values);
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end
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else
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begin
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VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values);
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end;
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end
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else if AnsiSameText(sl_Operand, 'XMEM64') then
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begin
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Item.OpNumber := il_Op;
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Item.OpTyp := otXMEM64;
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Item.OpActive := true;
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if UsePrefix then sl_Prefix := 'oword ';
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if x64 then
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begin
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VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64XMMIndex, Item.Values);
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end
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else
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begin
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VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32XMMIndex, Item.Values);
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end;
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end
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else if AnsiSameText(sl_Operand, 'YMEM32') then
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begin
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Item.OpNumber := il_Op;
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Item.OpTyp := otYMEM32;
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Item.OpActive := true;
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if UsePrefix then sl_Prefix := 'yword ';
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if x64 then
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begin
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VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values);
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end
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else
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begin
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VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values);
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end;
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end
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else if AnsiSameText(sl_Operand, 'YMEM64') then
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begin
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Item.OpNumber := il_Op;
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Item.OpTyp := otYMEM64;
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Item.OpActive := true;
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if UsePrefix then sl_Prefix := 'yword ';
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if x64 then
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begin
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VectorMemRegBaseIndexCombi(sl_prefix, FReg64Base, FReg64YMMIndex, Item.Values);
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end
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else
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begin
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VectorMemRegBaseIndexCombi(sl_prefix, FReg32Base, FReg32YMMIndex, Item.Values);
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end;
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end
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else
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begin
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Item.OpNumber := il_Op;
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@ -590,7 +668,8 @@ begin
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Item.OpActive := false;
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Item.Values.Add('');
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end;
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end
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end;
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sl_RegCombi := '';
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@ -755,6 +834,11 @@ begin
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FReg64Index := TStringList.Create;
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FReg6432Base := TStringList.Create;
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FReg6432Index := TStringList.Create;
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FReg32XMMIndex := TStringList.Create;
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FReg32YMMIndex := TStringList.Create;
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FReg64XMMIndex := TStringList.Create;
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FReg64YMMIndex := TStringList.Create;
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FReg32Base.Add('EAX');
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FReg32Base.Add('EBX');
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@ -840,6 +924,60 @@ begin
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FReg6432Index.Add('R13D');
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FReg6432Index.Add('R14D');
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FReg6432Index.Add('R15D');
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FReg32XMMIndex.ADD('XMM0');
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FReg32XMMIndex.ADD('XMM1');
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FReg32XMMIndex.ADD('XMM2');
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FReg32XMMIndex.ADD('XMM3');
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FReg32XMMIndex.ADD('XMM4');
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FReg32XMMIndex.ADD('XMM5');
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FReg32XMMIndex.ADD('XMM6');
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FReg32XMMIndex.ADD('XMM7');
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FReg32YMMIndex.ADD('YMM0');
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FReg32YMMIndex.ADD('YMM1');
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FReg32YMMIndex.ADD('YMM2');
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FReg32YMMIndex.ADD('YMM3');
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FReg32YMMIndex.ADD('YMM4');
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FReg32YMMIndex.ADD('YMM5');
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FReg32YMMIndex.ADD('YMM6');
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FReg32YMMIndex.ADD('YMM7');
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FReg64XMMIndex.ADD('XMM0');
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FReg64XMMIndex.ADD('XMM1');
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FReg64XMMIndex.ADD('XMM2');
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FReg64XMMIndex.ADD('XMM3');
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FReg64XMMIndex.ADD('XMM4');
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FReg64XMMIndex.ADD('XMM5');
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FReg64XMMIndex.ADD('XMM6');
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FReg64XMMIndex.ADD('XMM7');
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FReg64XMMIndex.ADD('XMM8');
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FReg64XMMIndex.ADD('XMM9');
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FReg64XMMIndex.ADD('XMM10');
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FReg64XMMIndex.ADD('XMM11');
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FReg64XMMIndex.ADD('XMM12');
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FReg64XMMIndex.ADD('XMM13');
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FReg64XMMIndex.ADD('XMM14');
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FReg64XMMIndex.ADD('XMM15');
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FReg64YMMIndex.ADD('YMM0');
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FReg64YMMIndex.ADD('YMM1');
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FReg64YMMIndex.ADD('YMM2');
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FReg64YMMIndex.ADD('YMM3');
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FReg64YMMIndex.ADD('YMM4');
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FReg64YMMIndex.ADD('YMM5');
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FReg64YMMIndex.ADD('YMM6');
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FReg64YMMIndex.ADD('YMM7');
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FReg64YMMIndex.ADD('YMM8');
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FReg64YMMIndex.ADD('YMM9');
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FReg64YMMIndex.ADD('YMM10');
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FReg64YMMIndex.ADD('YMM11');
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FReg64YMMIndex.ADD('YMM12');
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FReg64YMMIndex.ADD('YMM13');
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FReg64YMMIndex.ADD('YMM14');
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FReg64YMMIndex.ADD('YMM15');
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end;
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destructor TAsmTestGenerator.Destroy;
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@ -851,6 +989,11 @@ begin
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FreeAndNil(FReg6432Base);
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FreeAndNil(FReg6432Index);
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FreeAndNil(FReg32XMMIndex);
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FreeAndNil(FReg32YMMIndex);
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FreeAndNil(FReg64XMMIndex);
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FreeAndNil(FReg64YMMIndex);
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inherited;
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end;
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@ -880,6 +1023,51 @@ begin
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end;
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end;
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procedure TAsmTestGenerator.VectorMemRegBaseIndexCombi(const aPrefix: String;
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aSLBaseReg, aSLIndexReg, aRList: TStringList);
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var
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il_Base: integer;
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il_Index: integer;
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begin
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//for il_Index := 0 to aSLIndexReg.Count - 1 do
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//begin
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// aRList.Add(format(aPrefix + '[%s]', [aSLIndexReg[il_Index]]));
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//
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// aRList.Add(format(aPrefix + '[%s * 2]', [aSLIndexReg[il_Index]]));
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// aRList.Add(format(aPrefix + '[%s * 4]', [aSLIndexReg[il_Index]]));
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// aRList.Add(format(aPrefix + '[%s * 8]', [aSLIndexReg[il_Index]]));
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//
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// aRList.Add(format(aPrefix + '[%s * 2 + 16]', [aSLIndexReg[il_Index]]));
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// aRList.Add(format(aPrefix + '[%s * 4 + 32]', [aSLIndexReg[il_Index]]));
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// aRList.Add(format(aPrefix + '[%s * 8 + 48]', [aSLIndexReg[il_Index]]));
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//end;
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for il_Base := 0 to aSLBaseReg.Count - 1 do
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begin
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//aRList.Add(format(aPrefix + '[%s]', [aSLBaseReg[il_Base]]));
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for il_Index := 0 to aSLIndexReg.Count - 1 do
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begin
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aRList.Add(format(aPrefix + '[%s + %s]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
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aRList.Add(format(aPrefix + '[%s + %s * 2]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
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aRList.Add(format(aPrefix + '[%s + %s * 4]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
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aRList.Add(format(aPrefix + '[%s + %s * 8]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
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aRList.Add(format(aPrefix + '[%s + %s * 2 + 16]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
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aRList.Add(format(aPrefix + '[%s + %s * 4 + 32]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
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aRList.Add(format(aPrefix + '[%s + %s * 8 + 48]', [aSLBaseReg[il_Base], aSLIndexReg[il_Index]]));
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aRList.Add(format(aPrefix + '[%s + %s]', [aSLIndexReg[il_Index], aSLBaseReg[il_Base]]));
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aRList.Add(format(aPrefix + '[%s + %s + 16]', [aSLIndexReg[il_Index], aSLBaseReg[il_Base]]));
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end;
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end;
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end;
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class procedure TAsmTestGenerator.CalcTestData(aX64: boolean; const aInst, aOp1, aOp2, aOp3,
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aOp4: String; aSL: TStringList);
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var
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@ -773,6 +773,36 @@ begin
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FOpCodeList.Add('VFNMSUB132SS,1,1,XMMREG,XMMREG,XMMRM,');
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FOpCodeList.Add('VFNMSUB213SS,1,1,XMMREG,XMMREG,XMMRM,');
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FOpCodeList.Add('VFNMSUB231SS,1,1,XMMREG,XMMREG,XMMRM,');
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FOpCodeList.Add('VGATHERDPD,1,1,XMMREG,XMEM32,XMMREG,');
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FOpCodeList.Add('VGATHERDPD,1,1,YMMREG,XMEM32,YMMREG,');
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FOpCodeList.Add('VGATHERQPD,1,1,XMMREG,XMEM64,XMMREG,');
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FOpCodeList.Add('VGATHERQPD,1,1,YMMREG,YMEM64,YMMREG,');
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FOpCodeList.Add('VGATHERDPS,1,1,XMMREG,XMEM32,XMMREG,');
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FOpCodeList.Add('VGATHERDPS,1,1,YMMREG,YMEM32,YMMREG,');
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FOpCodeList.Add('VGATHERQPS,1,1,XMMREG,XMEM64,XMMREG,');
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FOpCodeList.Add('VGATHERQPS,1,1,XMMREG,YMEM64,XMMREG,');
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FOpCodeList.Add('VPGATHERDD,1,1,XMMREG,XMEM32,XMMREG,');
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FOpCodeList.Add('VPGATHERDD,1,1,YMMREG,YMEM32,YMMREG,');
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FOpCodeList.Add('VPGATHERQD,1,1,XMMREG,XMEM64,XMMREG,');
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FOpCodeList.Add('VPGATHERQD,1,1,XMMREG,YMEM64,XMMREG,');
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FOpCodeList.Add('VPGATHERDQ,1,1,XMMREG,XMEM32,XMMREG,');
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FOpCodeList.Add('VPGATHERDQ,1,1,YMMREG,XMEM32,YMMREG,');
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FOpCodeList.Add('VPGATHERQQ,1,1,XMMREG,XMEM64,XMMREG,');
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FOpCodeList.Add('VPGATHERQQ,1,1,YMMREG,YMEM64,YMMREG,');
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end;
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function TAVXTestGenerator.InternalMakeTestFiles(aX64: boolean; aDestPath, aFileExt: String;
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