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- removed due to BSD license header
git-svn-id: trunk@22286 -
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@ -7241,7 +7241,6 @@ rtl/android/jvm/java_sysh_android.inc svneol=native#text/plain
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rtl/android/jvm/rtl.cfg svneol=native#text/plain
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rtl/arm/arm.inc svneol=native#text/plain
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rtl/arm/armdefines.inc svneol=native#text/plain
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rtl/arm/divide.inc svneol=native#text/plain
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rtl/arm/int64p.inc svneol=native#text/plain
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rtl/arm/makefile.cpu svneol=native#text/plain
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rtl/arm/math.inc svneol=native#text/plain
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@ -1013,5 +1013,5 @@ begin
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end;
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{include hand-optimized assembler division code}
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{$i divide.inc}
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{ $i divide.inc}
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@ -1,185 +0,0 @@
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{
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Divide/modulo for Acorn RISC Machine
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... taken from a GP2X Ogg Tremor port by Dzz and converted to
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Pascal.
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Copyright (c) 2007, Daniel Mantione
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Copyright (c) 2006, Dzz
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Copyright (c) 2002, Xiph.org Foundation
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions
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are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of the Xiph.org Foundation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION
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OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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}
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{$ifndef FPC_SYSTEM_HAS_DIV_DWORD}
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{$define FPC_SYSTEM_HAS_DIV_DWORD}
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function fpc_div_dword(n,z:dword):dword;[public,alias: 'FPC_DIV_DWORD'];assembler;nostackframe;
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asm
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{$ifdef CPUARM_HAS_IDIV}
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udiv r0, r0, r1
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{$else}
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mov r3, #0
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rsbs r2, r0, r1, LSR#3
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bcc .Ldiv_3bits
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rsbs r2, r0, r1, LSR#8
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bcc .Ldiv_8bits
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mov r0, r0, LSL#8
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orr r3, r3, #0xFF000000
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rsbs r2, r0, r1, LSR#4
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bcc .Ldiv_4bits
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rsbs r2, r0, r1, LSR#8
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bcc .Ldiv_8bits
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mov r0, r0, LSL#8
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orr r3, r3, #0x00FF0000
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rsbs r2, r0, r1, LSR#8
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movcs r0, r0, LSL#8
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orrcs r3, r3, #0x0000FF00
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rsbs r2, r0, r1, LSR#4
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bcc .Ldiv_4bits
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rsbs r2, r0, #0
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bcs .Ldiv_by_0
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.Ldiv_loop:
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movcs r0, r0, LSR#8
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.Ldiv_8bits:
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rsbs r2, r0, r1, LSR#7
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subcs r1, r1, r0, LSL#7
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adc r3, r3, r3
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rsbs r2, r0, r1, LSR#6
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subcs r1, r1, r0, LSL#6
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adc r3, r3, r3
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rsbs r2, r0, r1, LSR#5
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subcs r1, r1, r0, LSL#5
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adc r3, r3, r3
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rsbs r2, r0, r1, LSR#4
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subcs r1, r1, r0, LSL#4
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adc r3, r3, r3
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.Ldiv_4bits:
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rsbs r2, r0, r1, LSR#3
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subcs r1, r1, r0, LSL#3
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adc r3, r3, r3
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.Ldiv_3bits:
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rsbs r2, r0, r1, LSR#2
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subcs r1, r1, r0, LSL#2
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adc r3, r3, r3
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rsbs r2, r0, r1, LSR#1
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subcs r1, r1, r0, LSL#1
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adc r3, r3, r3
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rsbs r2, r0, r1
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subcs r1, r1, r0
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adcs r3, r3, r3
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.Ldiv_next:
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bcs .Ldiv_loop
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mov r0, r3
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{$ifdef CPUARM_HAS_BX}
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bx lr
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{$else}
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mov pc, lr
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{$endif}
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.Ldiv_by_0:
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mov r0, #200
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mov r1, r11
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bl handleerrorframe
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{$ifdef CPUARM_HAS_BX}
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bx lr
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{$else}
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mov pc, lr
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{$endif}
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{$endif}
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end;
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{It is a compilerproc (systemh.inc), make an alias for internal use.}
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function fpc_div_dword(n,z:dword):dword;external name 'FPC_DIV_DWORD';
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{$endif}
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{$ifndef FPC_SYSTEM_HAS_DIV_LONGINT}
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{$define FPC_SYSTEM_HAS_DIV_LONGINT}
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function fpc_div_longint(n,z:longint):longint;[public,alias: 'FPC_DIV_LONGINT'];assembler;nostackframe;
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asm
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{$ifdef CPUARM_HAS_IDIV}
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sdiv r0, r0, r1
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{$else}
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stmfd sp!, {lr}
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ands r12, r0, #1<<31 (* r12:=r0 and $80000000 *)
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rsbmi r0, r0, #0 (* if signed(r0) then r0:=0-r0 *)
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eors r12, r12, r1, ASR#32 (* r12:=r12 xor (r1 asr 32) *)
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rsbcs r1, r1, #0 (* if signed(r12) then r1:=0-r1 *)
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bl fpc_div_dword
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movs r12, r12, LSL#1 (* carry:=sign(r12) *)
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rsbcs r0, r0, #0
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rsbmi r1, r1, #0
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ldmfd sp!, {pc}
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{$endif}
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end;
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{It is a compilerproc (systemh.inc), make an alias for internal use.}
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function fpc_div_longint(n,z:longint):longint;external name 'FPC_DIV_LONGINT';
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{$endif}
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{$ifndef FPC_SYSTEM_HAS_MOD_DWORD}
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{$define FPC_SYSTEM_HAS_MOD_DWORD}
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function fpc_mod_dword(n,z:dword):dword;[public,alias: 'FPC_MOD_DWORD'];assembler;nostackframe;
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asm
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{$ifdef CPUARM_HAS_IDIV}
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udiv r2, r0, r1
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mul r2,r1,r2
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sub r0,r0,r2
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{$else}
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stmfd sp!, {lr}
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bl fpc_div_dword
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mov r0, r1
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ldmfd sp!, {pc}
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{$endif}
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end;
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{It is a compilerproc (systemh.inc), make an alias for internal use.}
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function fpc_mod_dword(n,z:dword):dword;external name 'FPC_MOD_DWORD';
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{$endif}
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{$ifndef FPC_SYSTEM_HAS_MOD_LONGINT}
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{$define FPC_SYSTEM_HAS_MOD_LONGINT}
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function fpc_mod_longint(n,z:longint):longint;[public,alias: 'FPC_MOD_LONGINT'];assembler;nostackframe;
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asm
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{$ifdef CPUARM_HAS_IDIV}
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sdiv r2, r0, r1
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smull r2,r3,r1,r2
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sub r0,r0,r2
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{$else}
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stmfd sp!, {lr}
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bl fpc_div_longint
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mov r0, r1
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ldmfd sp!, {pc}
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{$endif}
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end;
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{It is a compilerproc (systemh.inc), make an alias for internal use.}
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function fpc_mod_longint(n,z:longint):longint;external name 'FPC_MOD_LONGINT';
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{$endif}
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