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* cr*, dr*, tr* registers are 64 bit on x86-64

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git-svn-id: trunk@18243 -
This commit is contained in:
florian 2011-08-17 11:42:11 +00:00
parent 8dc1ce55c1
commit 87696a4b70
4 changed files with 24 additions and 1 deletions
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1
.gitattributes vendored
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@ -9138,6 +9138,7 @@ tests/tbs/tb0575.pp svneol=native#text/plain
tests/tbs/tb0576.pp svneol=native#text/plain tests/tbs/tb0576.pp svneol=native#text/plain
tests/tbs/tb0577.pp svneol=native#text/plain tests/tbs/tb0577.pp svneol=native#text/plain
tests/tbs/tb0577a.pp svneol=native#text/plain tests/tbs/tb0577a.pp svneol=native#text/plain
tests/tbs/tb0578.pp svneol=native#text/pascal
tests/tbs/tb205.pp svneol=native#text/plain tests/tbs/tb205.pp svneol=native#text/plain
tests/tbs/ub0060.pp svneol=native#text/plain tests/tbs/ub0060.pp svneol=native#text/plain
tests/tbs/ub0069.pp svneol=native#text/plain tests/tbs/ub0069.pp svneol=native#text/plain

4
compiler/x86/aasmcpu.pas
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@ -92,7 +92,11 @@ interface
OT_REG_SMASK = otf_sub0 or otf_sub1 or otf_sub2 or otf_sub3; OT_REG_SMASK = otf_sub0 or otf_sub1 or otf_sub2 or otf_sub3;
{ register class 0: CRx, DRx and TRx } { register class 0: CRx, DRx and TRx }
{$ifdef x86_64}
OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS64;
{$else x86_64}
OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS32; OT_REG_CDT = OT_REGISTER or otf_reg_cdt or OT_BITS32;
{$endif x86_64}
OT_REG_CREG = OT_REG_CDT or otf_sub0; { CRn } OT_REG_CREG = OT_REG_CDT or otf_sub0; { CRn }
OT_REG_DREG = OT_REG_CDT or otf_sub1; { DRn } OT_REG_DREG = OT_REG_CDT or otf_sub1; { DRn }
OT_REG_TREG = OT_REG_CDT or otf_sub2; { TRn } OT_REG_TREG = OT_REG_CDT or otf_sub2; { TRn }

6
compiler/x86/cpubase.pas
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@ -348,7 +348,11 @@ implementation
R_SPECIALREGISTER : R_SPECIALREGISTER :
case reg of case reg of
NR_CS,NR_DS,NR_ES,NR_SS,NR_FS,NR_GS: NR_CS,NR_DS,NR_ES,NR_SS,NR_FS,NR_GS:
reg_cgsize:=OS_16 reg_cgsize:=OS_16;
{$ifdef x86_64}
NR_DR0..NR_TR7:
reg_cgsize:=OS_64;
{$endif x86_64}
else else
reg_cgsize:=OS_32 reg_cgsize:=OS_32
end end

14
tests/tbs/tb0578.pp Normal file
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@ -0,0 +1,14 @@
{ %OPT=-Sew }
{ %CPU=x86_64 }
{ %NORUN }
{$asmmode intel}
begin
asm
mov rax,cr0
mov rax,cr4
mov rax,tr3
mov rax,cr3
mov rax,dr0
end;
end.