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* arm thumb2 supports only left shifted index registers up to 3 bits

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git-svn-id: trunk@25346 -
This commit is contained in:
florian 2013-08-23 15:22:49 +00:00
parent 6df2917d93
commit 8884f1c0bf
1 changed files with 8 additions and 1 deletions
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9
compiler/arm/aoptcpu.pas
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@ -1216,7 +1216,8 @@ Implementation
add r1, r3, #imm
ldr r0, [r1, r2, lsl #2]
}
if (taicpu(p).opcode = A_MOV) and
if (not(current_settings.cputype in cpu_thumb)) and
(taicpu(p).opcode = A_MOV) and
(taicpu(p).ops = 3) and
(taicpu(p).oper[1]^.typ = top_reg) and
(taicpu(p).oper[2]^.typ = top_shifterop) and
@ -1224,6 +1225,12 @@ Implementation
it is also extremly unlikely to be emitted this way}
(taicpu(p).oper[2]^.shifterop^.shiftmode <> SM_RRX) and
(taicpu(p).oper[2]^.shifterop^.shiftimm <> 0) and
{ thumb2 allows only lsl #0..#3 }
(not(current_settings.cputype in cpu_thumb2) or
((taicpu(p).oper[2]^.shifterop^.shiftimm in [0..3]) and
(taicpu(p).oper[2]^.shifterop^.shiftmode=SM_LSL)
)
) and
(taicpu(p).oppostfix = PF_NONE) and
GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) and
{Only LDR, LDRB, STR, STRB can handle scaled register indexing}