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m68k: added the byterev and ff1 CF ISAA+/ISAC instructions, also added byterev as a CPU capability

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git-svn-id: trunk@28679 -
This commit is contained in:
Károly Balogh 2014-09-16 01:39:02 +00:00
parent fbd5828624
commit 8acc260a09
3 changed files with 6 additions and 5 deletions
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2
compiler/m68k/cpubase.pas
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@ -67,7 +67,7 @@ unit cpubase;
{ mc64040 instructions }
a_move16,
{ coldfire v4 instructions }
a_mov3q,a_mvz,a_mvs,a_sats,
a_mov3q,a_mvz,a_mvs,a_sats,a_byterev,a_ff1,
{ fpu processor instructions - directly supported only. }
{ ieee aware and misc. condition codes not supported }
a_fabs,a_fadd,

7
compiler/m68k/cpuinfo.pas
View File

@ -108,7 +108,8 @@ type
CPUM68K_HAS_CAS, { CPU supports the CAS instruction }
CPUM68K_HAS_TAS, { CPU supports the TAS instruction }
CPUM68K_HAS_BRAL, { CPU supports the BRA.L/Bcc.L instructions }
CPUM68K_HAS_ROLROR { CPU supports the ROL/ROR and ROXL/ROXR instructions }
CPUM68K_HAS_ROLROR, { CPU supports the ROL/ROR and ROXL/ROXR instructions }
CPUM68K_HAS_BYTEREV { CPU supports the BYTEREV instruction }
);
const
@ -118,9 +119,9 @@ const
{ cpu_68020 } [CPUM68K_HAS_DBRA,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR],
{ cpu_68040 } [CPUM68K_HAS_DBRA,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL,CPUM68K_HAS_ROLROR],
{ cpu_isaa } [],
{ cpu_isaap } [CPUM68K_HAS_BRAL],
{ cpu_isaap } [CPUM68K_HAS_BRAL,CPUM68K_HAS_BYTEREV],
{ cpu_isab } [CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL],
{ cpu_isac } [CPUM68K_HAS_TAS]
{ cpu_isac } [CPUM68K_HAS_TAS,CPUM68K_HAS_BYTEREV]
);
{ all CPUs commonly called "coldfire" }

2
compiler/m68k/itcpugas.pas
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@ -61,7 +61,7 @@ interface
{ mc64040 instructions }
'move16',
{ coldfire v4 instructions }
'mov3q','mvz','mvs','sats',
'mov3q','mvz','mvs','sats','byterev','ff1',
{ fpu processor instructions - directly supported only. }
{ ieee aware and misc. condition codes not supported }
'fabs','fadd',