mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-11-20 02:34:04 +01:00
* more stuff converted
This commit is contained in:
florian
parent
c9dfdcfbcd
commit
8b7be9c5dd
@ -20,7 +20,7 @@
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****************************************************************************
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}
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unit ncal;
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unit nmat;
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interface
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@ -29,44 +29,364 @@ unit ncal;
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type
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tmoddivnode = class(tbinopnode)
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function pass_1 : tnode;override;
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end;
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tshlshrnode = class(tbinopnode)
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function pass_1 : tnode;override;
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end;
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tunaryminusnode = class(tunarynode)
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constructor create(expr : tnode);virtual;
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function pass_1 : tnode;override;
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end;
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tnotnode = class(tunarynode)
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constructor create(expr : tnode);virtual;
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constructor create(expr : tnode);virtual;
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function pass_1 : tnode;override;
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end;
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var
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cmoddivnode : class of tmoddivnode;
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cshlshrnode : class of tshlshrnode;
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cunaryminusnode : class of tunaryminusnode;
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cnotnode : class of cnotnode;
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cnotnode : class of tnotnode;
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implementation
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uses
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globtype,systems,tokens,
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cobjects,verbose,globals,
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symconst,symtable,aasm,types,
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htypechk,pass_1,cpubase,cpuinfo,
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{$ifdef newcg}
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cgbase,
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{$else newcg}
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hcodegen,
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{$endif newcg}
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{ for isbinaryoverloaded function }
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nadd;
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{****************************************************************************
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TMODDIVNODE
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****************************************************************************}
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function tmoddivnode.pass_1 : tnode;
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var
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t : tnode
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rv,lv : tconstexprint;
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rd,ld : pdef;
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begin
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firstpass(left);
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right.set_varstate(true);
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firstpass(right);
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right.set_varstate(true);
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if codegenerror then
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exit;
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if isbinaryoverloaded(p) then
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exit;
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{ check for division by zero }
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rv:=right.value;
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lv:=left.value;
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if is_constintnode(right) and (rv=0) then
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begin
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Message(parser_e_division_by_zero);
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{ recover }
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rv:=1;
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end;
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if is_constintnode(left) and is_constintnode(right) then
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begin
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case treetype of
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modn:
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t:=genintconstnode(lv mod rv);
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divn:
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t:=genintconstnode(lv div rv);
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end;
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firstpass(t);
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pass_1:=t;
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exit;
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end;
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if (left.resulttype^.deftype=orddef) and (right.resulttype^.deftype=orddef) and
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(is_64bitint(left.resulttype) or is_64bitint(right.resulttype)) then
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begin
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rd:=right.resulttype;
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ld:=left.resulttype;
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if (porddef(rd)^.typ=s64bit) or (porddef(ld)^.typ=s64bit) then
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begin
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if (porddef(ld)^.typ<>s64bit) then
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begin
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left:=gentypeconvnode(left,cs64bitdef);
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firstpass(left);
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end;
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if (porddef(rd)^.typ<>s64bit) then
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begin
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right:=gentypeconvnode(right,cs64bitdef);
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firstpass(right);
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end;
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calcregisters(p,2,0,0);
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end
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else if (porddef(rd)^.typ=u64bit) or (porddef(ld)^.typ=u64bit) then
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begin
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if (porddef(ld)^.typ<>u64bit) then
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begin
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left:=gentypeconvnode(left,cu64bitdef);
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firstpass(left);
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end;
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if (porddef(rd)^.typ<>u64bit) then
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begin
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right:=gentypeconvnode(right,cu64bitdef);
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firstpass(right);
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end;
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calcregisters(p,2,0,0);
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end;
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resulttype:=left.resulttype;
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end
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else
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begin
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if not(right.resulttype^.deftype=orddef) or
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not(porddef(right.resulttype)^.typ in [s32bit,u32bit]) then
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right:=gentypeconvnode(right,s32bitdef);
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if not(left.resulttype^.deftype=orddef) or
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not(porddef(left.resulttype)^.typ in [s32bit,u32bit]) then
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left:=gentypeconvnode(left,s32bitdef);
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firstpass(left);
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firstpass(right);
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{$ifdef cardinalmulfix}
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{ if we divide a u32bit by a positive constant, the result is also u32bit (JM) }
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if (left.resulttype^.deftype = orddef) and
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(left.resulttype^.deftype = orddef) then
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begin
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if (porddef(left.resulttype)^.typ = u32bit) and
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is_constintnode(right) and
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{ (porddef(right.resulttype)^.typ <> u32bit) and}
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(right.value > 0) then
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begin
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right := gentypeconvnode(right,u32bitdef);
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firstpass(right);
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end;
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{ adjust also the left resulttype if necessary }
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if (porddef(right.resulttype)^.typ = u32bit) and
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is_constintnode(left) and
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{ (porddef(left.resulttype)^.typ <> u32bit) and}
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(left.value > 0) then
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begin
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left := gentypeconvnode(left,u32bitdef);
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firstpass(left);
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end;
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end;
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{$endif cardinalmulfix}
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{ the resulttype depends on the right side, because the left becomes }
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{ always 64 bit }
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resulttype:=right.resulttype;
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if codegenerror then
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exit;
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left_right_max(p);
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if left.registers32<=right.registers32 then
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inc(registers32);
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end;
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location.loc:=LOC_REGISTER;
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end;
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{****************************************************************************
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TSHLSHRNODE
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****************************************************************************}
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function tshlshrnode.pass_1 : tnode;
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var
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t : tnode;
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regs : longint;
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begin
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firstpass(left);
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set_varstate(left,true);
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firstpass(right);
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set_varstate(right,true);
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if codegenerror then
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exit;
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if isbinaryoverloaded(p) then
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exit;
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if is_constintnode(left) and is_constintnode(right) then
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begin
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case treetype of
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shrn:
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t:=genintconstnode(left.value shr right.value);
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shln:
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t:=genintconstnode(left.value shl right.value);
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end;
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firstpass(t);
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pass_1:=t;
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exit;
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end;
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{ 64 bit ints have their own shift handling }
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if not(is_64bitint(left.resulttype)) then
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begin
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left:=gentypeconvnode(left,s32bitdef);
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firstpass(left);
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regs:=1;
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resulttype:=s32bitdef;
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end
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else
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begin
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resulttype:=left.resulttype;
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regs:=2;
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end;
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right:=gentypeconvnode(right,s32bitdef);
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firstpass(right);
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if codegenerror then
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exit;
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if (right.treetype<>ordconstn) then
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inc(regs);
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calcregisters(p,regs,0,0);
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location.loc:=LOC_REGISTER;
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end;
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{****************************************************************************
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TUNARYMINUSNODE
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****************************************************************************}
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constructor tnotnode.create(expr : tnode);
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constructor tunaryminusnode.create(expr : tnode);
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begin
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inherited create(notn,expr);
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inherited create(unaryminusn,expr);
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end;
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function tunaryminusnode.pass_1 : tnode;
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var
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t : tnode;
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minusdef : pprocdef;
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begin
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pass_1:=nil;
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firstpass(left);
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set_varstate(left,true);
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registers32:=left.registers32;
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registersfpu:=left.registersfpu;
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{$ifdef SUPPORT_MMX}
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registersmmx:=left.registersmmx;
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{$endif SUPPORT_MMX}
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resulttype:=left.resulttype;
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if codegenerror then
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exit;
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if is_constintnode(left) then
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begin
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t:=genintconstnode(-left.value);
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firstpass(t);
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pass_1:=t;
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exit;
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end;
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{ nasm can not cope with negativ reals !! }
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if is_constrealnode(left)
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{$ifdef i386}
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and not(aktoutputformat in [as_i386_nasmcoff,as_i386_nasmelf,as_i386_nasmobj])
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{$endif i386}
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then
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begin
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t:=genrealconstnode(-left.value_real,bestrealdef^);
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firstpass(t);
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pass_1:=t;
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exit;
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end;
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if (left.resulttype^.deftype=floatdef) then
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begin
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if pfloatdef(left.resulttype)^.typ=f32bit then
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begin
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if (left.location.loc<>LOC_REGISTER) and
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(registers32<1) then
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registers32:=1;
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location.loc:=LOC_REGISTER;
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end
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else
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location.loc:=LOC_FPU;
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end
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{$ifdef SUPPORT_MMX}
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else if (cs_mmx in aktlocalswitches) and
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is_mmx_able_array(left.resulttype) then
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begin
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if (left.location.loc<>LOC_MMXREGISTER) and
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(registersmmx<1) then
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registersmmx:=1;
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{ if saturation is on, left.resulttype isn't
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"mmx able" (FK)
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if (cs_mmx_saturation in aktlocalswitches^) and
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(porddef(parraydef(resulttype)^.definition)^.typ in
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[s32bit,u32bit]) then
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CGMessage(type_e_mismatch);
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}
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end
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{$endif SUPPORT_MMX}
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else if is_64bitint(left.resulttype) then
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begin
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firstpass(left);
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registersfpu:=left.registersfpu;
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{$ifdef SUPPORT_MMX}
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registersmmx:=left.registersmmx;
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{$endif SUPPORT_MMX}
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registers32:=left.registers32;
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if codegenerror then
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exit;
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if (left.location.loc<>LOC_REGISTER) and
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(registers32<2) then
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registers32:=2;
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location.loc:=LOC_REGISTER;
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resulttype:=left.resulttype;
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end
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else if (left.resulttype^.deftype=orddef) then
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begin
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left:=gentypeconvnode(left,s32bitdef);
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firstpass(left);
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registersfpu:=left.registersfpu;
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{$ifdef SUPPORT_MMX}
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registersmmx:=left.registersmmx;
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{$endif SUPPORT_MMX}
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registers32:=left.registers32;
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if codegenerror then
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exit;
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if (left.location.loc<>LOC_REGISTER) and
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(registers32<1) then
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registers32:=1;
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location.loc:=LOC_REGISTER;
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resulttype:=left.resulttype;
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end
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else
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begin
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if assigned(overloaded_operators[_minus]) then
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minusdef:=overloaded_operators[_minus]^.definition
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else
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minusdef:=nil;
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while assigned(minusdef) do
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begin
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if is_equal(pparaitem(minusdef^.para^.first)^.paratype.def,left.resulttype) and
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(pparaitem(minusdef^.para^.first)^.next=nil) then
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begin
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t:=gencallnode(overloaded_operators[_minus],nil);
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t.left:=gencallparanode(left,nil);
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left:=nil;
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firstpass(t);
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pass_1:=t;
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exit;
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end;
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minusdef:=minusdef^.nextoverloaded;
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end;
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CGMessage(type_e_mismatch);
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end;
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end;
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{****************************************************************************
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TNOTNODE
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****************************************************************************}
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@ -77,6 +397,115 @@ unit ncal;
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inherited create(notn,expr);
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end;
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function tnotnode.pass_1 : tnode;
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var
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t : tnode;
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notdef : pprocdef;
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begin
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firstpass(left);
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set_varstate(left,true);
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if codegenerror then
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exit;
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if (left.treetype=ordconstn) then
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begin
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if is_boolean(left.resulttype) then
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{ here we do a boolena(byte(..)) type cast because }
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{ boolean(<int64>) is buggy in 1.00 }
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t:=genordinalconstnode(byte(not(boolean(byte(left.value)))),left.resulttype)
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else
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t:=genordinalconstnode(not(left.value),left.resulttype);
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firstpass(t);
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pass_1:=t;
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exit;
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end;
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resulttype:=left.resulttype;
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location.loc:=left.location.loc;
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{$ifdef SUPPORT_MMX}
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registersmmx:=left.registersmmx;
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{$endif SUPPORT_MMX}
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if is_boolean(resulttype) then
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begin
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registers32:=left.registers32;
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if (location.loc in [LOC_REFERENCE,LOC_MEM,LOC_CREGISTER]) then
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begin
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location.loc:=LOC_REGISTER;
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if (registers32<1) then
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registers32:=1;
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end;
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{ before loading it into flags we need to load it into
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a register thus 1 register is need PM }
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{$ifdef i386}
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if left.location.loc<>LOC_JUMP then
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location.loc:=LOC_FLAGS;
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{$endif def i386}
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end
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else
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{$ifdef SUPPORT_MMX}
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if (cs_mmx in aktlocalswitches) and
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is_mmx_able_array(left.resulttype) then
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begin
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if (left.location.loc<>LOC_MMXREGISTER) and
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(registersmmx<1) then
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registersmmx:=1;
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end
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else
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{$endif SUPPORT_MMX}
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if is_64bitint(left.resulttype) then
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begin
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registers32:=left.registers32;
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if (location.loc in [LOC_REFERENCE,LOC_MEM,LOC_CREGISTER]) then
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begin
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location.loc:=LOC_REGISTER;
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if (registers32<2) then
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registers32:=2;
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end;
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end
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else if is_integer(left.resulttype) then
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begin
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left:=gentypeconvnode(left,s32bitdef);
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firstpass(left);
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if codegenerror then
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exit;
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resulttype:=left.resulttype;
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registers32:=left.registers32;
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{$ifdef SUPPORT_MMX}
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registersmmx:=left.registersmmx;
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{$endif SUPPORT_MMX}
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if (left.location.loc<>LOC_REGISTER) and
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(registers32<1) then
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registers32:=1;
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location.loc:=LOC_REGISTER;
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end
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else
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begin
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if assigned(overloaded_operators[_op_not]) then
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notdef:=overloaded_operators[_op_not]^.definition
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else
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notdef:=nil;
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while assigned(notdef) do
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begin
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if is_equal(pparaitem(notdef^.para^.first)^.paratype.def,left.resulttype) and
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(pparaitem(notdef^.para^.first)^.next=nil) then
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begin
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t:=gencallnode(overloaded_operators[_op_not],nil);
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t.left:=gencallparanode(left,nil);
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left:=nil;
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firstpass(t);
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pass_1:=t;
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exit;
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end;
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notdef:=notdef^.nextoverloaded;
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end;
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CGMessage(type_e_mismatch);
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end;
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registersfpu:=left.registersfpu;
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end;
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begin
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cmoddivnode:=tmoddivnode;
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cshlshrnode:=tshlshrnode;
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@ -85,7 +514,9 @@ begin
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end.
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{
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$Log$
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Revision 1.1 2000-09-20 21:35:12 florian
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* initial revision
|
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Revision 1.2 2000-09-22 22:09:54 florian
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* more stuff converted
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Revision 1.1 2000/09/20 21:35:12 florian
|
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* initial revision
|
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}
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