From 8c0d9b581cd26fc2d0112ab72ba1d4c2e37491c8 Mon Sep 17 00:00:00 2001
From: Jonas Maebe <jonas@freepascal.org>
Date: Wed, 30 Mar 2016 20:04:31 +0000
Subject: [PATCH]   * don't write the destination register in
 a_load_ref_reg_unaligned() before     the reference has been used for the
 last time, as the destination     register could be the base or index
 register of the reference

git-svn-id: trunk@33393 -
---
 .gitattributes             |  1 +
 compiler/aarch64/cgcpu.pas |  3 ++-
 tests/tbs/tb0618.pp        | 42 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 45 insertions(+), 1 deletion(-)
 create mode 100644 tests/tbs/tb0618.pp

diff --git a/.gitattributes b/.gitattributes
index cf1193a6e1..ec271f768e 100644
--- a/.gitattributes
+++ b/.gitattributes
@@ -10875,6 +10875,7 @@ tests/tbs/tb0614.pp svneol=native#text/pascal
 tests/tbs/tb0615.pp svneol=native#text/pascal
 tests/tbs/tb0616.pp svneol=native#text/pascal
 tests/tbs/tb0617.pp svneol=native#text/pascal
+tests/tbs/tb0618.pp svneol=native#text/plain
 tests/tbs/tb205.pp svneol=native#text/plain
 tests/tbs/tb610.pp svneol=native#text/pascal
 tests/tbs/tb613.pp svneol=native#text/plain
diff --git a/compiler/aarch64/cgcpu.pas b/compiler/aarch64/cgcpu.pas
index d8e41d6cbc..ef75405d7e 100644
--- a/compiler/aarch64/cgcpu.pas
+++ b/compiler/aarch64/cgcpu.pas
@@ -812,7 +812,7 @@ implementation
         if fromsize in [OS_64,OS_S64] then
           begin
             { split into two 32 bit loads }
-            hreg1:=makeregsize(register,OS_32);
+            hreg1:=getintregister(list,OS_32);
             hreg2:=getintregister(list,OS_32);
             if target_info.endian=endian_big then
               begin
@@ -831,6 +831,7 @@ implementation
                 inc(href.offset,4);
                 a_load_ref_reg(list,OS_32,OS_32,href,hreg2);
               end;
+            a_load_reg_reg(list,OS_32,OS_64,hreg1,register);
             list.concat(taicpu.op_reg_reg_const_const(A_BFI,register,makeregsize(hreg2,OS_64),32,32));
           end
        else
diff --git a/tests/tbs/tb0618.pp b/tests/tbs/tb0618.pp
new file mode 100644
index 0000000000..518c3c6a09
--- /dev/null
+++ b/tests/tbs/tb0618.pp
@@ -0,0 +1,42 @@
+type
+     PStreamRec= ^TStreamRec;
+
+     TStreamRec = Packed Record
+       ObjType : byte;
+       Next : PStreamRec;
+     end;
+
+const
+   BaseRec : PStreamRec= nil;
+
+   RType1 : TStreamRec = (
+    ObjType : 79
+   );
+   RType2 : TStreamRec = (
+    objtype : 80
+   );
+
+
+procedure RegisterType(var R : TStreamRec);
+var
+  P : PStreamRec;
+
+begin
+  P := BaseRec;
+  while (P <> nil) and (P^.Objtype <> R.ObjType) do
+    P:=P^.Next;
+  if not assigned(P) then
+    begin
+      R.Next:=BaseRec;
+      BaseRec:=@R;
+    end;
+  { nothing to do here
+  else
+    P:=@R; }
+end;
+
+begin
+  RegisterType(Rtype1);
+  RegisterType(RType2);
+end.
+