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+ implemented OP_SHR,OP_SHL,OP_SAR,OP_ROL and OP_ROR in tcg8086.a_op_const_ref

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git-svn-id: trunk@35945 -
This commit is contained in:
nickysn 2017-04-25 11:06:12 +00:00
parent c2ec612f1f
commit 8c200fcfba
1 changed files with 52 additions and 0 deletions
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52
compiler/i8086/cgcpu.pas
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@ -804,6 +804,7 @@ unit cgcpu;
var var
tmpref: treference; tmpref: treference;
op1,op2: TAsmOp; op1,op2: TAsmOp;
tmpreg: TRegister;
begin begin
optimize_op_const(size, op, a); optimize_op_const(size, op, a);
tmpref:=ref; tmpref:=ref;
@ -901,6 +902,57 @@ unit cgcpu;
else else
a_op_const_ref(list,op,OS_16,aint(a shr 16),tmpref); a_op_const_ref(list,op,OS_16,aint(a shr 16),tmpref);
end; end;
OP_SHR,OP_SHL,OP_SAR:
begin
a:=a and 31;
if a=1 then
begin
case op of
OP_SHR:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
inc(tmpref.offset, 2);
list.concat(taicpu.op_const_ref(A_SHR,S_W,1,tmpref));
dec(tmpref.offset, 2);
list.concat(taicpu.op_const_ref(A_RCR,S_W,1,tmpref));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
OP_SAR:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
inc(tmpref.offset, 2);
list.concat(taicpu.op_const_ref(A_SAR,S_W,1,tmpref));
dec(tmpref.offset, 2);
list.concat(taicpu.op_const_ref(A_RCR,S_W,1,tmpref));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
OP_SHL:
begin
cg.a_reg_alloc(list,NR_DEFAULTFLAGS);
list.concat(taicpu.op_const_ref(A_SHL,S_W,1,tmpref));
inc(tmpref.offset, 2);
list.concat(taicpu.op_const_ref(A_RCL,S_W,1,tmpref));
cg.a_reg_dealloc(list,NR_DEFAULTFLAGS);
end;
else
internalerror(2015042501);
end;
end
else
begin
tmpreg:=getintregister(list,size);
a_load_ref_reg(list,size,size,ref,tmpreg);
a_op_const_reg(list,Op,size,a,tmpreg);
a_load_reg_ref(list,size,size,tmpreg,ref);
end;
end;
OP_ROL,OP_ROR:
begin
tmpreg:=getintregister(list,size);
a_load_ref_reg(list,size,size,ref,tmpreg);
a_op_const_reg(list,Op,size,a,tmpreg);
a_load_reg_ref(list,size,size,tmpreg,ref);
end;
else else
internalerror(2013050802); internalerror(2013050802);
end; end;