From 8e45bb133dda3e4417c9427f1cc2c11739447b38 Mon Sep 17 00:00:00 2001
From: florian <florian@freepascal.org>
Date: Thu, 20 Feb 2025 22:41:35 +0100
Subject: [PATCH]   + RV64GCB CPU type

---
 compiler/riscv/agrvgas.pas   | 4 ++--
 compiler/riscv64/cpuinfo.pas | 9 ++++++---
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/compiler/riscv/agrvgas.pas b/compiler/riscv/agrvgas.pas
index abaf6d8025..c2328f0df7 100644
--- a/compiler/riscv/agrvgas.pas
+++ b/compiler/riscv/agrvgas.pas
@@ -237,8 +237,8 @@ unit agrvgas;
           ('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32imafdc','rv32imafd','rv32ecfd','rv32gc')
 {$endif RISCV32}
 {$ifdef RISCV64}
-          ('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc'),
-          ('','rv64imafdc','rv64imafd','rv64imfd','rv64ifd','rv64imafdc','rv64imafd','rv64gc')
+          ('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc','rv64gcb'),
+          ('','rv64imafdc','rv64imafd','rv64imfd','rv64ifd','rv64imafdc','rv64imafd','rv64gc','rv64gcb')
 {$endif RISCV64}
         );
       begin
diff --git a/compiler/riscv64/cpuinfo.pas b/compiler/riscv64/cpuinfo.pas
index 4ef4e0112b..bff84e38e6 100644
--- a/compiler/riscv64/cpuinfo.pas
+++ b/compiler/riscv64/cpuinfo.pas
@@ -40,7 +40,8 @@ type
     cpu_rv64i,
     cpu_rv64imafdc,
     cpu_rv64imafd,
-    cpu_rv64gc
+    cpu_rv64gc,
+    cpu_rv64gcb
   );
 
   tfputype =
@@ -96,7 +97,8 @@ Const
     'RV64I',
     'RV64IMAFDC',
     'RV64IMAFD',
-    'RV64GC'
+    'RV64GC',
+    'RV64GCB'
     );
 
   fputypestr: array[tfputype] of string[8] = (
@@ -157,7 +159,8 @@ Const
        { cpu_rv64i      } [],
        { cpu_rv64imafdc } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_F,CPURV_HAS_D],
        { cpu_rv64imafd  } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_F,CPURV_HAS_D],
-       { cpu_rv64gc     } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_CSR_INSTRUCTIONS,CPURV_HAS_FETCH_FENCE,CPURV_HAS_F,CPURV_HAS_D]
+       { cpu_rv64gc     } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_CSR_INSTRUCTIONS,CPURV_HAS_FETCH_FENCE,CPURV_HAS_F,CPURV_HAS_D],
+       { cpu_rv64gcb    } [CPURV_HAS_MUL,CPURV_HAS_ATOMIC,CPURV_HAS_COMPACT,CPURV_HAS_CSR_INSTRUCTIONS,CPURV_HAS_FETCH_FENCE,CPURV_HAS_F,CPURV_HAS_D,CPURV_HAS_ZBA,CPURV_HAS_ZBB,CPURV_HAS_ZBS]
      );
 
 implementation