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* Xtensa: tcgcpu.g_concatcopy makes use of loop extensions if available

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git-svn-id: trunk@46781 -
This commit is contained in:
florian 2020-09-05 20:25:29 +00:00
parent 451bb09e8f
commit 8ef6372340
2 changed files with 24 additions and 10 deletions
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29
compiler/xtensa/cgcpu.pas
View File

@ -1053,15 +1053,28 @@ implementation
tmpreg1 := GetIntRegister(list, OS_INT); tmpreg1 := GetIntRegister(list, OS_INT);
a_load_const_reg(list, OS_INT, Count, countreg); a_load_const_reg(list, OS_INT, Count, countreg);
current_asmdata.getjumplabel(lab); current_asmdata.getjumplabel(lab);
a_label(list, lab); if CPUXTENSA_HAS_LOOPS in cpu_capabilities[current_settings.cputype] then
list.concat(taicpu.op_reg_ref(A_L32I, tmpreg1, src)); begin
list.concat(taicpu.op_reg_ref(A_S32I, tmpreg1, dst)); list.concat(taicpu.op_reg_sym(A_LOOP, countreg, lab));
list.concat(taicpu.op_reg_reg_const(A_ADDI, src.base, src.base, 4)); list.concat(taicpu.op_reg_ref(A_L32I, tmpreg1, src));
list.concat(taicpu.op_reg_reg_const(A_ADDI, dst.base, dst.base, 4)); list.concat(taicpu.op_reg_ref(A_S32I, tmpreg1, dst));
list.concat(taicpu.op_reg_reg_const(A_ADDI, countreg, countreg, -1)); list.concat(taicpu.op_reg_reg_const(A_ADDI, src.base, src.base, 4));
a_cmp_const_reg_label(list,OS_INT,OC_NE,0,countreg,lab); list.concat(taicpu.op_reg_reg_const(A_ADDI, dst.base, dst.base, 4));
a_label(list, lab);
end
else
begin
a_label(list, lab);
list.concat(taicpu.op_reg_ref(A_L32I, tmpreg1, src));
list.concat(taicpu.op_reg_ref(A_S32I, tmpreg1, dst));
list.concat(taicpu.op_reg_reg_const(A_ADDI, src.base, src.base, 4));
list.concat(taicpu.op_reg_reg_const(A_ADDI, dst.base, dst.base, 4));
list.concat(taicpu.op_reg_reg_const(A_ADDI, countreg, countreg, -1));
a_cmp_const_reg_label(list,OS_INT,OC_NE,0,countreg,lab);
{ keep the registers alive }
list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
end;
{ keep the registers alive } { keep the registers alive }
list.concat(taicpu.op_reg_reg(A_MOV,countreg,countreg));
list.concat(taicpu.op_reg_reg(A_MOV,src.base,src.base)); list.concat(taicpu.op_reg_reg(A_MOV,src.base,src.base));
list.concat(taicpu.op_reg_reg(A_MOV,dst.base,dst.base)); list.concat(taicpu.op_reg_reg(A_MOV,dst.base,dst.base));
len := len mod 4; len := len mod 4;

5
compiler/xtensa/cpuinfo.pas
View File

@ -139,7 +139,8 @@ Const
CPUXTENSA_HAS_SEXT, CPUXTENSA_HAS_SEXT,
CPUXTENSA_HAS_BOOLEAN_OPTION, CPUXTENSA_HAS_BOOLEAN_OPTION,
CPUXTENSA_HAS_MUL32HIGH, CPUXTENSA_HAS_MUL32HIGH,
CPUXTENSA_HAS_DIV CPUXTENSA_HAS_DIV,
CPUXTENSA_HAS_LOOPS
); );
tfpuflags = tfpuflags =
@ -153,7 +154,7 @@ Const
( (
{ cpu_none } [], { cpu_none } [],
{ cpu_lx106 } [], { cpu_lx106 } [],
{ cpu_lx6 } [CPUXTENSA_REGWINDOW, CPUXTENSA_HAS_SEXT, CPUXTENSA_HAS_BOOLEAN_OPTION, CPUXTENSA_HAS_MUL32HIGH, CPUXTENSA_HAS_DIV] { cpu_lx6 } [CPUXTENSA_REGWINDOW, CPUXTENSA_HAS_SEXT, CPUXTENSA_HAS_BOOLEAN_OPTION, CPUXTENSA_HAS_MUL32HIGH, CPUXTENSA_HAS_DIV, CPUXTENSA_HAS_LOOPS]
); );
fpu_capabilities : array[tfputype] of set of tfpuflags = fpu_capabilities : array[tfputype] of set of tfpuflags =