From 8ffb72ddd0ff843e830641aed26fd6c6bdc126c2 Mon Sep 17 00:00:00 2001 From: florian Date: Wed, 4 Sep 2019 16:36:54 +0000 Subject: [PATCH] * another missing part of r42916 ... git-svn-id: trunk@42919 - --- .gitattributes | 1 + compiler/aarch64/ncpucon.pas | 89 ++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 compiler/aarch64/ncpucon.pas diff --git a/.gitattributes b/.gitattributes index 4e36c8aca0..8244fba179 100644 --- a/.gitattributes +++ b/.gitattributes @@ -29,6 +29,7 @@ compiler/aarch64/hlcgcpu.pas svneol=native#text/plain compiler/aarch64/itcpugas.pas svneol=native#text/plain compiler/aarch64/ncpuadd.pas svneol=native#text/plain compiler/aarch64/ncpucnv.pas svneol=native#text/plain +compiler/aarch64/ncpucon.pas svneol=native#text/pascal compiler/aarch64/ncpuinl.pas svneol=native#text/plain compiler/aarch64/ncpumat.pas svneol=native#text/plain compiler/aarch64/ncpumem.pas svneol=native#text/plain diff --git a/compiler/aarch64/ncpucon.pas b/compiler/aarch64/ncpucon.pas new file mode 100644 index 0000000000..e29c30fc42 --- /dev/null +++ b/compiler/aarch64/ncpucon.pas @@ -0,0 +1,89 @@ +{ + Copyright (c) 2005 by Florian Klaempfl + + Code generation for const nodes on the AArch64 + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + + **************************************************************************** +} +unit ncpucon; + +{$i fpcdefs.inc} + +interface + + uses + node,ncgcon,cpubase; + + type + taarch64realconstnode = class(tcgrealconstnode) + function pass_1 : tnode;override; + procedure pass_generate_code;override; + end; + + implementation + + uses + verbose, + globtype,globals, + cpuinfo, + aasmbase,aasmtai,aasmdata,aasmcpu, + symdef, + defutil, + cgbase,cgutils,cgobj, + procinfo, + ncon; + +{***************************************************************************** + TARMREALCONSTNODE +*****************************************************************************} + + function taarch64realconstnode.pass_1 : tnode; + begin + result:=nil; + if IsFloatImmediate(tfloatdef(resultdef).floattype,value_real) then + expectloc:=LOC_MMREGISTER + else + result:=Inherited pass_1; + end; + + + procedure taarch64realconstnode.pass_generate_code; + var + hreg : TRegister; + begin + if IsFloatImmediate(tfloatdef(resultdef).floattype,value_real) then + begin + location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef)); + location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size); + current_asmdata.CurrAsmList.concat(taicpu.op_reg_realconst(A_FMOV, + location.register,value_real)); + end + else if value_real=0.0 then + begin + location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef)); + location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size); + hreg:=newreg(R_MMREGISTER,getsupreg(location.register),R_SUBMM16B); + current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_EOR, + hreg,hreg,hreg)); + end + else + Inherited pass_generate_code; + end; + +begin + crealconstnode:=taarch64realconstnode; +end.