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* RiscV: unified cpu initialization and FPU exception handling, resolves #38893

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git-svn-id: trunk@49374 -
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florian 2021-05-15 20:53:56 +00:00
parent a714cfafb8
commit 90afbc8114
4 changed files with 96 additions and 78 deletions
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1
.gitattributes vendored
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@ -12039,6 +12039,7 @@ rtl/qnx/qnx.inc svneol=native#text/plain
rtl/qnx/rtldefs.inc svneol=native#text/plain
rtl/qnx/signal.inc svneol=native#text/plain
rtl/qnx/system.pp svneol=native#text/plain
rtl/riscv/riscv.inc svneol=native#text/plain
rtl/riscv32/cpuh.inc svneol=native#text/plain
rtl/riscv32/int64p.inc svneol=native#text/plain
rtl/riscv32/makefile.cpu svneol=native#text/plain

89
rtl/riscv/riscv.inc Normal file
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@ -0,0 +1,89 @@
{
This file is part of the Free Pascal run time library.
Copyright (c) 2008 by the Free Pascal development team.
Processor dependent implementation for the system unit for
RiscV which is common to all RiscV types
See the file COPYING.FPC, included in this distribution,
for details about the copyright.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
**********************************************************************}
{****************************************************************************
fpu exception related stuff
****************************************************************************}
{$ifdef FPUFD}
const
fpu_nx = 1 shl 0;
fpu_uf = 1 shl 1;
fpu_of = 1 shl 2;
fpu_dz = 1 shl 3;
fpu_nv = 1 shl 4;
function getfflags: sizeuint; nostackframe; assembler;
asm
frflags a0
end;
procedure setfflags(flags : sizeuint); nostackframe; assembler;
asm
fsflags a0
end;
procedure RaisePendingExceptions;
var
fflags : sizeuint;
f: TFPUException;
begin
fflags:=getfflags;
if (fflags and fpu_dz) <> 0 then
float_raise(exZeroDivide);
if (fflags and fpu_of) <> 0 then
float_raise(exOverflow);
if (fflags and fpu_uf) <> 0 then
float_raise(exUnderflow);
if (fflags and fpu_nv) <> 0 then
float_raise(exInvalidOp);
if (fflags and fpu_nx) <> 0 then
float_raise(exPrecision);
{ now the soft float exceptions }
for f in softfloat_exception_flags do
float_raise(f);
end;
procedure fpc_throwfpuexception;[public,alias:'FPC_THROWFPUEXCEPTION'];
var
fflags : sizeuint;
begin
fflags:=getfflags;
{ check, if the exception is masked }
if ((fflags and fpu_dz) <> 0) and (exZeroDivide in softfloat_exception_mask) then
fflags:=fflags and not(fpu_dz);
if ((fflags and fpu_of) <> 0) and (exOverflow in softfloat_exception_mask) then
fflags:=fflags and not(fpu_of);
if ((fflags and fpu_uf) <> 0) and (exUnderflow in softfloat_exception_mask) then
fflags:=fflags and not(fpu_uf);
if ((fflags and fpu_nv) <> 0) and (exInvalidOp in softfloat_exception_mask) then
fflags:=fflags and not(fpu_nv);
if ((fflags and fpu_nx) <> 0) and (exPrecision in softfloat_exception_mask) then
fflags:=fflags and not(fpu_nx);
setfflags(fflags);
if fflags<>0 then
RaisePendingExceptions;
end;
{$endif FPUFD}
procedure fpc_cpuinit;{$ifdef SYSTEMINLINE}inline;{$endif}
begin
softfloat_exception_mask:=[exPrecision,exUnderflow];
end;

8
rtl/riscv32/riscv32.inc
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@ -4,7 +4,7 @@
Copyright (c) 2008 by the Free Pascal development team.
Processor dependent implementation for the system unit for
AVR
RiscV32
See the file COPYING.FPC, included in this distribution,
for details about the copyright.
@ -15,10 +15,8 @@
**********************************************************************}
procedure fpc_cpuinit;{$ifdef SYSTEMINLINE}inline;{$endif}
begin
end;
{ Common RiscV stuff }
{$I ../riscv/riscv.inc}
{$IFNDEF INTERNAL_BACKTRACE}
{$define FPC_SYSTEM_HAS_GET_FRAME}

76
rtl/riscv64/riscv64.inc
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@ -4,7 +4,7 @@
Copyright (c) 2008 by the Free Pascal development team.
Processor dependent implementation for the system unit for
AVR
RiscV64
See the file COPYING.FPC, included in this distribution,
for details about the copyright.
@ -15,78 +15,8 @@
**********************************************************************}
{****************************************************************************
fpu exception related stuff
****************************************************************************}
{$ifdef FPUFD}
const
fpu_nx = 1 shl 0;
fpu_uf = 1 shl 1;
fpu_of = 1 shl 2;
fpu_dz = 1 shl 3;
fpu_nv = 1 shl 4;
function getfflags: sizeuint; nostackframe; assembler;
asm
frflags a0
end;
procedure setfflags(flags : sizeuint); nostackframe; assembler;
asm
fsflags a0
end;
procedure RaisePendingExceptions;
var
fflags : sizeuint;
f: TFPUException;
begin
fflags:=getfflags;
if (fflags and fpu_dz) <> 0 then
float_raise(exZeroDivide);
if (fflags and fpu_of) <> 0 then
float_raise(exOverflow);
if (fflags and fpu_uf) <> 0 then
float_raise(exUnderflow);
if (fflags and fpu_nv) <> 0 then
float_raise(exInvalidOp);
if (fflags and fpu_nx) <> 0 then
float_raise(exPrecision);
{ now the soft float exceptions }
for f in softfloat_exception_flags do
float_raise(f);
end;
procedure fpc_throwfpuexception;[public,alias:'FPC_THROWFPUEXCEPTION'];
var
fflags : sizeuint;
begin
fflags:=getfflags;
{ check, if the exception is masked }
if ((fflags and fpu_dz) <> 0) and (exZeroDivide in softfloat_exception_mask) then
fflags:=fflags and not(fpu_dz);
if ((fflags and fpu_of) <> 0) and (exOverflow in softfloat_exception_mask) then
fflags:=fflags and not(fpu_of);
if ((fflags and fpu_uf) <> 0) and (exUnderflow in softfloat_exception_mask) then
fflags:=fflags and not(fpu_uf);
if ((fflags and fpu_nv) <> 0) and (exInvalidOp in softfloat_exception_mask) then
fflags:=fflags and not(fpu_nv);
if ((fflags and fpu_nx) <> 0) and (exPrecision in softfloat_exception_mask) then
fflags:=fflags and not(fpu_nx);
setfflags(fflags);
if fflags<>0 then
RaisePendingExceptions;
end;
{$endif FPUFD}
procedure fpc_cpuinit;{$ifdef SYSTEMINLINE}inline;{$endif}
begin
softfloat_exception_mask:=[exPrecision,exUnderflow];
end;
{ Common RiscV stuff }
{$I ../riscv/riscv.inc}
{****************************************************************************
stack frame related stuff