diff --git a/compiler/riscv/cgrv.pas b/compiler/riscv/cgrv.pas
index f2ffaa858c..ed5d9f9403 100644
--- a/compiler/riscv/cgrv.pas
+++ b/compiler/riscv/cgrv.pas
@@ -564,6 +564,8 @@ unit cgrv;
           OS_64,
           OS_S64: op:=A_LD;
 {$else}
+          OS_64,OS_S64, { This only happens if tosize is smaller than fromsize }
+          { We can therefore only consider the low 32-bit of the 64bit value }
           OS_32,
           OS_S32: op:=A_LW;
 {$endif}
@@ -594,7 +596,7 @@ unit cgrv;
                 else
                   list.concat(taicpu.op_reg_const(A_LUI,register,(a shr 12) and $FFFFF));
 
-                list.concat(taicpu.op_reg_reg_const(A_ADDI,register,register,SarSmallint(a shl 4,4)));
+                list.concat(taicpu.op_reg_reg_const(A_ADDI,register,register,SarSmallint(smallint(a shl 4),4)));
               end;
           end;
       end;
diff --git a/compiler/riscv/rgcpu.pas b/compiler/riscv/rgcpu.pas
index e24821575a..1eef36f4d4 100644
--- a/compiler/riscv/rgcpu.pas
+++ b/compiler/riscv/rgcpu.pas
@@ -70,7 +70,7 @@ unit rgcpu;
               helplist.concat(taicpu.op_reg_const(A_LUI,hreg,((spilltemp.offset shr 12)+1) and $FFFFF))
             else
               helplist.concat(taicpu.op_reg_const(A_LUI,hreg,(spilltemp.offset shr 12) and $FFFFF));
-            helplist.concat(taicpu.op_reg_reg_const(A_ADDI,hreg,hreg,SarSmallint(spilltemp.offset shl 4,4)));
+            helplist.concat(taicpu.op_reg_reg_const(A_ADDI,hreg,hreg,SarSmallint(smallint(spilltemp.offset shl 4),4)));
 
             helplist.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,hreg,spilltemp.base));
 
@@ -105,7 +105,7 @@ unit rgcpu;
               helplist.concat(taicpu.op_reg_const(A_LUI,hreg,((spilltemp.offset shr 12)+1) and $FFFFF))
             else
               helplist.concat(taicpu.op_reg_const(A_LUI,hreg,(spilltemp.offset shr 12) and $FFFFF));
-            helplist.concat(taicpu.op_reg_reg_const(A_ADDI,hreg,hreg,SarSmallint(spilltemp.offset shl 4,4)));
+            helplist.concat(taicpu.op_reg_reg_const(A_ADDI,hreg,hreg,SarSmallint(smallint(spilltemp.offset shl 4),4)));
 
             helplist.concat(taicpu.op_reg_reg_reg(A_ADD,hreg,hreg,spilltemp.base));
 
diff --git a/compiler/riscv64/cgcpu.pas b/compiler/riscv64/cgcpu.pas
index d953575800..cd973987f6 100644
--- a/compiler/riscv64/cgcpu.pas
+++ b/compiler/riscv64/cgcpu.pas
@@ -161,7 +161,7 @@ implementation
                 else
                   list.concat(taicpu.op_reg_const(A_LUI,register,(a shr 12) and $FFFFF));
 
-                list.concat(taicpu.op_reg_reg_const(A_ADDIW,register,register,SarSmallint(a shl 4,4)));
+                list.concat(taicpu.op_reg_reg_const(A_ADDIW,register,register,SarSmallint(smallint(a shl 4),4)));
               end
             else
               begin