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* Reworked i386 division by constant optimization to reuse code from powerpc64. The algorithm is slightly different, signed version is one instruction shorter, unsigned one is one instruction longer (typically). The new algorithm is easily scalable for x86_64 target, unlike the old one.
git-svn-id: trunk@27884 -
This commit is contained in:
sergei
parent
90d2009a31
commit
92cf25b9a5
@ -61,16 +61,6 @@ implementation
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TI386MODDIVNODE
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*****************************************************************************}
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function log2(i : dword) : dword;
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begin
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result:=0;
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i:=i shr 1;
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while i<>0 do
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begin
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i:=i shr 1;
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inc(result);
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end;
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end;
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procedure ti386moddivnode.pass_generate_code;
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@ -80,8 +70,10 @@ implementation
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hl:Tasmlabel;
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op:Tasmop;
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e : longint;
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d,l,r,s,m,a,n,t : dword;
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m_low,m_high,j,k : qword;
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d,m: dword;
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s: byte;
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sm: aint;
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m_add: boolean;
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begin
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secondpass(left);
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if codegenerror then
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@ -147,74 +139,28 @@ implementation
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if is_signed(left.resultdef) then
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begin
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e:=tordconstnode(right).value.svalue;
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d:=abs(e);
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{ Determine algorithm (a), multiplier (m), and shift factor (s) for 32-bit
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signed integer division. Based on: Granlund, T.; Montgomery, P.L.:
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"Division by Invariant Integers using Multiplication". SIGPLAN Notices,
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Vol. 29, June 1994, page 61.
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}
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l:=log2(d);
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j:=qword($80000000) mod qword(d);
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k:=(qword(1) shl (32+l)) div (qword($80000000-j));
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m_low:=((qword(1)) shl (32+l)) div d;
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m_high:=(((qword(1)) shl (32+l)) + k) div d;
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while ((m_low shr 1) < (m_high shr 1)) and (l > 0) do
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begin
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m_low:=m_low shr 1;
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m_high:=m_high shr 1;
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dec(l);
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end;
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m:=dword(m_high);
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s:=l;
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if (m_high shr 31)<>0 then
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a:=1
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else
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a:=0;
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calc_divconst_magic_signed(32,e,sm,s);
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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emit_const_reg(A_MOV,S_L,aint(m),NR_EAX);
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emit_const_reg(A_MOV,S_L,sm,NR_EAX);
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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emit_reg(A_IMUL,S_L,hreg1);
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emit_reg_reg(A_MOV,S_L,hreg1,NR_EAX);
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if a<>0 then
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begin
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emit_reg_reg(A_ADD,S_L,NR_EAX,NR_EDX);
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{
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printf ("; dividend: memory location or register other than EAX or EDX\n");
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printf ("\n");
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printf ("MOV EAX, 0%08LXh\n", m);
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printf ("IMUL dividend\n");
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printf ("MOV EAX, dividend\n");
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printf ("ADD EDX, EAX\n");
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if (s) printf ("SAR EDX, %d\n", s);
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printf ("SHR EAX, 31\n");
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printf ("ADD EDX, EAX\n");
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if (e < 0) printf ("NEG EDX\n");
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printf ("\n");
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printf ("; quotient now in EDX\n");
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}
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end;
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{
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printf ("; dividend: memory location of register other than EAX or EDX\n");
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printf ("\n");
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printf ("MOV EAX, 0%08LXh\n", m);
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printf ("IMUL dividend\n");
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printf ("MOV EAX, dividend\n");
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if (s) printf ("SAR EDX, %d\n", s);
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printf ("SHR EAX, 31\n");
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printf ("ADD EDX, EAX\n");
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if (e < 0) printf ("NEG EDX\n");
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printf ("\n");
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printf ("; quotient now in EDX\n");
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}
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if s<>0 then
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emit_const_reg(A_SAR,S_L,s,NR_EDX);
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emit_const_reg(A_SHR,S_L,31,NR_EAX);
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emit_reg_reg(A_ADD,S_L,NR_EAX,NR_EDX);
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if e<0 then
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emit_reg(A_NEG,S_L,NR_EDX);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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{ only the high half of result is used }
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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{ add or subtract dividend }
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if (e>0) and (sm<0) then
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emit_reg_reg(A_ADD,S_L,hreg1,NR_EDX)
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else if (e<0) and (sm>0) then
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emit_reg_reg(A_SUB,S_L,hreg1,NR_EDX);
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{ shift if necessary }
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if (s<>0) then
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emit_const_reg(A_SAR,S_L,s,NR_EDX);
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{ extract and add the sign bit }
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if (e<0) then
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emit_reg_reg(A_MOV,S_L,NR_EDX,hreg1);
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{ if e>=0, hreg1 still contains dividend }
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emit_const_reg(A_SHR,S_L,31,hreg1);
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emit_reg_reg(A_ADD,S_L,hreg1,NR_EDX);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_EDX,location.register)
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end
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@ -230,83 +176,22 @@ implementation
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end
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else
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begin
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{ Reduce divisor until it becomes odd }
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n:=0;
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t:=d;
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while (t and 1)=0 do
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begin
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t:=t shr 1;
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inc(n);
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end;
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{ Generate m, s for algorithm 0. Based on: Granlund, T.; Montgomery,
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P.L.: "Division by Invariant Integers using Multiplication".
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SIGPLAN Notices, Vol. 29, June 1994, page 61.
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}
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l:=log2(t)+1;
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j:=qword($ffffffff) mod qword(t);
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k:=(qword(1) shl (32+l)) div (qword($ffffffff-j));
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m_low:=((qword(1)) shl (32+l)) div t;
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m_high:=(((qword(1)) shl (32+l)) + k) div t;
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while ((m_low shr 1) < (m_high shr 1)) and (l>0) do
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begin
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m_low:=m_low shr 1;
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m_high:=m_high shr 1;
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l:=l-1;
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end;
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if (m_high shr 32)=0 then
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begin
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m:=dword(m_high);
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s:=l;
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a:=0;
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end
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{ Generate m, s for algorithm 1. Based on: Magenheimer, D.J.; et al:
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"Integer Multiplication and Division on the HP Precision Architecture".
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IEEE Transactions on Computers, Vol 37, No. 8, August 1988, page 980.
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}
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else
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begin
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s:=log2(t);
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m_low:=(qword(1) shl (32+s)) div qword(t);
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r:=dword(((qword(1)) shl (32+s)) mod qword(t));
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if (r < ((t>>1)+1)) then
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m:=dword(m_low)
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else
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m:=dword(m_low)+1;
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a:=1;
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end;
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{ Reduce multiplier for either algorithm to smallest possible }
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while (m and 1)=0 do
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begin
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m:=m shr 1;
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dec(s);
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end;
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{ Adjust multiplier for reduction of even divisors }
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inc(s,n);
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calc_divconst_magic_unsigned(32,d,m,m_add,s);
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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emit_const_reg(A_MOV,S_L,aint(m),NR_EAX);
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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emit_reg(A_MUL,S_L,hreg1);
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if a<>0 then
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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if m_add then
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begin
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{
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printf ("; dividend: register other than EAX or memory location\n");
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printf ("\n");
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printf ("MOV EAX, 0%08lXh\n", m);
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printf ("MUL dividend\n");
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printf ("ADD EAX, 0%08lXh\n", m);
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printf ("ADC EDX, 0\n");
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if (s) printf ("SHR EDX, %d\n", s);
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printf ("\n");
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printf ("; quotient now in EDX\n");
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}
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emit_const_reg(A_ADD,S_L,aint(m),NR_EAX);
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emit_const_reg(A_ADC,S_L,0,NR_EDX);
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emit_reg_reg(A_SUB,S_L,NR_EDX,hreg1);
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emit_const_reg(A_SHR,S_L,1,hreg1);
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emit_reg_reg(A_ADD,S_L,hreg1,NR_EDX);
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dec(s);
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end;
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if s<>0 then
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emit_const_reg(A_SHR,S_L,aint(s),NR_EDX);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EDX);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_EAX);
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_INT,OS_INT,NR_EDX,location.register)
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end;
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