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* Improved the comment.

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git-svn-id: trunk@40586 -
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yury 2018-12-18 13:23:52 +00:00
parent fdcb12d9f6
commit 92e579a294
1 changed files with 2 additions and 2 deletions
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4
compiler/arm/aoptcpu.pas
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@ -443,11 +443,11 @@ Implementation
For example: For example:
ldr reg2,[reg1, xxx]! ldr reg2,[reg1, xxx]!
mov reg1,reg2 mov reg1,reg2
is translated to: must be translated to:
ldr reg1,[reg1, xxx] ldr reg1,[reg1, xxx]
Preindexing must be removed there, since the same register is used as the base and as the target. Preindexing must be removed there, since the same register is used as the base and as the target.
It is not allowed for ARM CPU and produces wrong results. } Such case is not allowed for ARM CPU and produces crash. }
if (taicpu(p).opcode = A_LDR) and (taicpu(p).oper[1]^.typ = top_ref) if (taicpu(p).opcode = A_LDR) and (taicpu(p).oper[1]^.typ = top_ref)
and (taicpu(movp).oper[0]^.reg = taicpu(p).oper[1]^.ref^.base) and (taicpu(movp).oper[0]^.reg = taicpu(p).oper[1]^.ref^.base)
then then