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+ fp-armv8 fpu type added

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This commit is contained in:
florian 2021-11-06 11:00:53 +01:00
parent 9feafc7bd7
commit 9423d5e390
3 changed files with 15 additions and 7 deletions
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8
compiler/arm/aasmcpu.pas
View File

@ -166,11 +166,12 @@ uses
IF_ARMv7M = $00F00000;
IF_ARMv7EM = $01000000;
IF_FPMASK = $00000F00;
IF_FPMASK = $c0000F00;
IF_FPA = $00000100;
IF_VFPv2 = $00000200;
IF_VFPv3 = $00000400;
IF_VFPv4 = $00000800;
IF_VFPv5 = $80000000;
{ if the instruction can change in a second pass }
IF_PASS2 = $80000000;
@ -2246,8 +2247,9 @@ implementation
{ fpu_vfpv4 } IF_VFPv2 or IF_VFPv3 or IF_VFPv4,
{ fpu_vfpv4 } IF_VFPv2 or IF_VFPv3 or IF_VFPv4,
{ fpu_neon_vfpv4 } IF_VFPv2 or IF_VFPv3 or IF_VFPv4 or IF_NEON,
{ fpu_fpv5_d16 } IF_VFPv2 or IF_VFPv3 or IF_VFPv4,
{ fpu_fpv5_sp_d16} IF_VFPv2 or IF_VFPv3 or IF_VFPv4
{ fpu_fpv5_d16 } IF_VFPv2 or IF_VFPv3 or IF_VFPv4 or IF_VFPv5,
{ fpu_fpv5_sp_d16} IF_VFPv2 or IF_VFPv3 or IF_VFPv4 or IF_VFPv5,
{ fpu_fp_armv8 } IF_VFPv2 or IF_VFPv3 or IF_VFPv4 or IF_VFPv5
);
begin
fArmVMask:=Masks[current_settings.cputype] or FPUMasks[current_settings.fputype];

12
compiler/arm/cpuinfo.pas
View File

@ -76,7 +76,8 @@ Type
fpu_fpv4_sp_d16, { 32 registers single precision, for load/store/move they can be accessed as 16 double registers }
fpu_neon_vfpv4,
fpu_fpv5_d16,
fpu_fpv5_sp_d16
fpu_fpv5_sp_d16,
fpu_fp_armv8
{ when new elements added afterwards, update
class procedure tarmnodeutils.InsertObjectInfo; in narmutil.pas }
);
@ -97,7 +98,8 @@ Const
'fpu=fpv4-sp-d16',
'fpu=neon-vfpv4',
'fpu=fpv5-sp-d16',
'fpu=fpv5-d16'
'fpu=fpv5-d16',
'fpu=fp-armv8'
);
Type
@ -592,7 +594,8 @@ Const
'FPV4_SP_D16',
'NEON_VFPV4',
'FPV5_D16',
'FPV5_SP_D16'
'FPV5_SP_D16',
'FP_ARMV8'
);
@ -1137,7 +1140,8 @@ Const
{ fpu_fpv4_sp_d16 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
{ fpu_neon_vfpv4 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_NEON,FPUARM_HAS_FMA],
{ fpu_fpv5_d16 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
{ fpu_fpv5_sp_d16 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA]
{ fpu_fpv5_sp_d16 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_32REGS,FPUARM_HAS_VFP_DOUBLE_MOVLDST,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA],
{ fpu_fp_armv8 } [FPUARM_HAS_VFP_EXTENSION,FPUARM_HAS_VFP_DOUBLE,FPUARM_HAS_32REGS,FPUARM_HAS_VMOV_CONST,FPUARM_HAS_FMA]
);
{ contains all CPU supporting any kind of thumb instruction set }

2
compiler/arm/narmutil.pas
View File

@ -221,6 +221,8 @@ interface
fpu_fpv5_sp_d16,
fpu_fpv5_d16:
current_asmdata.asmlists[al_start].Concat(tai_eabi_attribute.create(Tag_FP_Arch,8));
fpu_fp_armv8:
current_asmdata.asmlists[al_start].Concat(tai_eabi_attribute.create(Tag_FP_Arch,7));
{ else not needed anymore PM 2020/04/13
Internalerror(2019100603); }
end;