+ added all used instructions to armins.dat

* first clean up of armins.dat

git-svn-id: trunk@1065 -

compiler/arm/aasmcpu.pas

@@ -37,25 +37,98 @@ uses
       { "mov reg,reg" source operand number }
       O_MOV_DEST = 0;
 
+      { Operand types }
+      OT_NONE      = $00000000;
+
+      OT_BITS8     = $00000001;  { size, and other attributes, of the operand  }
+      OT_BITS16    = $00000002;
+      OT_BITS32    = $00000004;
+      OT_BITS64    = $00000008;  { FPU only  }
+      OT_BITS80    = $00000010;
+      OT_FAR       = $00000020;  { this means 16:16 or 16:32, like in CALL/JMP }
+      OT_NEAR      = $00000040;
+      OT_SHORT     = $00000080;
+      OT_BITSTINY  = $00000100;  { fpu constant }
+
+      OT_SIZE_MASK = $000000FF;  { all the size attributes  }
+      OT_NON_SIZE  = longint(not OT_SIZE_MASK);
+
+      OT_SIGNED    = $00000100;  { the operand need to be signed -128-127 }
+
+      OT_TO        = $00000200;  { operand is followed by a colon  }
+                                 { reverse effect in FADD, FSUB &c  }
+      OT_COLON     = $00000400;
+
+      OT_REGISTER  = $00001000;
+      OT_IMMEDIATE = $00002000;
+      OT_REGLIST   = $00008000;
+      OT_IMM8      = $00002001;
+      OT_IMM16     = $00002002;
+      OT_IMM32     = $00002004;
+      OT_IMM64     = $00002008;
+      OT_IMM80     = $00002010;
+      OT_IMMTINY   = $00002100;
+      OT_IMMEDIATEFPU = OT_IMMTINY;
+
+      OT_REGMEM    = $00200000;  { for r/m, ie EA, operands  }
+      OT_REGNORM   = $00201000;  { 'normal' reg, qualifies as EA  }
+      OT_REG8      = $00201001;
+      OT_REG16     = $00201002;
+      OT_REG32     = $00201004;
+      OT_REG64     = $00201008;
+      OT_MMXREG    = $00201008;  { MMX registers  }
+      OT_XMMREG    = $00201010;  { Katmai registers  }
+      OT_MEMORY    = $00204000;  { register number in 'basereg'  }
+      OT_MEM8      = $00204001;
+      OT_MEM16     = $00204002;
+      OT_MEM32     = $00204004;
+      OT_MEM64     = $00204008;
+      OT_MEM80     = $00204010;
+      OT_FPUREG    = $01000000;  { floating point stack registers  }
+      OT_REG_SMASK = $00070000;  { special register operands: these may be treated differently  }
+                                 { a mask for the following  }
+
+      OT_MEM_OFFS  = $00604000;  { special type of EA  }
+                                 { simple [address] offset  }
+      OT_ONENESS   = $00800000;  { special type of immediate operand  }
+                                 { so UNITY == IMMEDIATE | ONENESS  }
+      OT_UNITY     = $00802000;  { for shift/rotate instructions  }
+
+      instabentries = {$i armnop.inc}
+
       maxinfolen = 5;
 
       IF_NONE   = $00000000;
 
       IF_ARMMASK    = $000F0000;
+      IF_ARM7       = $00070000;
+      IF_FPMASK     = $00F00000;
+      IF_FPA        = $00100000;
+
       { if the instruction can change in a second pass }
       IF_PASS2  = longint($80000000);
 
     type
+      TInsTabCache=array[TasmOp] of longint;
+      PInsTabCache=^TInsTabCache;
+
       tinsentry = record
         opcode  : tasmop;
         ops     : byte;
-        optypes : array[0..2] of longint;
+        optypes : array[0..3] of longint;
         code    : array[0..maxinfolen] of char;
         flags   : longint;
       end;
 
       pinsentry=^tinsentry;
 
+    const
+      InsTab : array[0..instabentries-1] of TInsEntry={$i armtab.inc}
+
+    var
+      InsTabCache : PInsTabCache;
+
+    type
       taicpu = class(tai_cpu_abstract)
          oppostfix : TOpPostfix;
          roundingmode : troundingmode;
@@ -101,7 +174,8 @@ uses
          procedure ResetPass1;
          procedure ResetPass2;
          function  CheckIfValid:boolean;
-         function  Pass1(offset:longint):longint;virtual;
+         function GetString:string;
+         function Pass1(offset:longint):longint;virtual;
          procedure Pass2(objdata:TAsmObjectdata);virtual;
       protected
          procedure ppuloadoper(ppufile:tcompilerppufile;var o:toper);override;
@@ -363,8 +437,6 @@ implementation
       end;
 
 
-{ ****************************** newra stuff *************************** }
-
     function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
       begin
         { allow the register allocator to remove unnecessary moves }
@@ -416,7 +488,7 @@ implementation
         case opcode of
           A_ADC,A_ADD,A_AND,
           A_EOR,A_CLZ,
-          A_LDR,A_LDRB,A_LDRD,A_LDRBT,A_LDRH,A_LDRSB,
+          A_LDR,A_LDRB,A_LDRBT,A_LDRH,A_LDRSB,
           A_LDRSH,A_LDRT,
           A_MOV,A_MVN,A_MLA,A_MUL,
           A_ORR,A_RSB,A_RSC,A_SBC,A_SUB,
@@ -445,7 +517,7 @@ implementation
               result:=operand_write
             else
               result:=operand_read;
-          A_STR,A_STRB,A_STRBT,A_STRD,
+          A_STR,A_STRB,A_STRBT,
           A_STRH,A_STRT,A_STF,A_SFM:
             { important is what happens with the involved registers }
             if opnr=0 then
@@ -563,6 +635,163 @@ implementation
       end;
 
 
+(*
+      Floating point instruction format information, taken from the linux kernel
+      ARM Floating Point Instruction Classes
+      | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
+      |c o n d|1 1 0 P|U|u|W|L|   Rn  |v|  Fd |0|0|0|1|  o f f s e t  | CPDT
+      |c o n d|1 1 0 P|U|w|W|L|   Rn  |x|  Fd |0|0|1|0|  o f f s e t  | CPDT (copro 2)
+      | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
+      |c o n d|1 1 1 0|a|b|c|d|e|  Fn |j|  Fd |0|0|0|1|f|g|h|0|i|  Fm | CPDO
+      |c o n d|1 1 1 0|a|b|c|L|e|  Fn |   Rd  |0|0|0|1|f|g|h|1|i|  Fm | CPRT
+      |c o n d|1 1 1 0|a|b|c|1|e|  Fn |1|1|1|1|0|0|0|1|f|g|h|1|i|  Fm | comparisons
+      | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
+
+      CPDT            data transfer instructions
+                      LDF, STF, LFM (copro 2), SFM (copro 2)
+
+      CPDO            dyadic arithmetic instructions
+                      ADF, MUF, SUF, RSF, DVF, RDF,
+                      POW, RPW, RMF, FML, FDV, FRD, POL
+
+      CPDO            monadic arithmetic instructions
+                      MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
+                      SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
+
+      CPRT            joint arithmetic/data transfer instructions
+                      FIX (arithmetic followed by load/store)
+                      FLT (load/store followed by arithmetic)
+                      CMF, CNF CMFE, CNFE (comparisons)
+                      WFS, RFS (write/read floating point status register)
+                      WFC, RFC (write/read floating point control register)
+
+      cond            condition codes
+      P               pre/post index bit: 0 = postindex, 1 = preindex
+      U               up/down bit: 0 = stack grows down, 1 = stack grows up
+      W               write back bit: 1 = update base register (Rn)
+      L               load/store bit: 0 = store, 1 = load
+      Rn              base register
+      Rd              destination/source register
+      Fd              floating point destination register
+      Fn              floating point source register
+      Fm              floating point source register or floating point constant
+
+      uv              transfer length (TABLE 1)
+      wx              register count (TABLE 2)
+      abcd            arithmetic opcode (TABLES 3 & 4)
+      ef              destination size (rounding precision) (TABLE 5)
+      gh              rounding mode (TABLE 6)
+      j               dyadic/monadic bit: 0 = dyadic, 1 = monadic
+      i               constant bit: 1 = constant (TABLE 6)
+      */
+
+      /*
+      TABLE 1
+      +-------------------------+---+---+---------+---------+
+      |  Precision              | u | v | FPSR.EP | length  |
+      +-------------------------+---+---+---------+---------+
+      | Single                  | 0 | 0 |    x    | 1 words |
+      | Double                  | 1 | 1 |    x    | 2 words |
+      | Extended                | 1 | 1 |    x    | 3 words |
+      | Packed decimal          | 1 | 1 |    0    | 3 words |
+      | Expanded packed decimal | 1 | 1 |    1    | 4 words |
+      +-------------------------+---+---+---------+---------+
+      Note: x = don't care
+      */
+
+      /*
+      TABLE 2
+      +---+---+---------------------------------+
+      | w | x | Number of registers to transfer |
+      +---+---+---------------------------------+
+      | 0 | 1 |  1                              |
+      | 1 | 0 |  2                              |
+      | 1 | 1 |  3                              |
+      | 0 | 0 |  4                              |
+      +---+---+---------------------------------+
+      */
+
+      /*
+      TABLE 3: Dyadic Floating Point Opcodes
+      +---+---+---+---+----------+-----------------------+-----------------------+
+      | a | b | c | d | Mnemonic | Description           | Operation             |
+      +---+---+---+---+----------+-----------------------+-----------------------+
+      | 0 | 0 | 0 | 0 | ADF      | Add                   | Fd := Fn + Fm         |
+      | 0 | 0 | 0 | 1 | MUF      | Multiply              | Fd := Fn * Fm         |
+      | 0 | 0 | 1 | 0 | SUF      | Subtract              | Fd := Fn - Fm         |
+      | 0 | 0 | 1 | 1 | RSF      | Reverse subtract      | Fd := Fm - Fn         |
+      | 0 | 1 | 0 | 0 | DVF      | Divide                | Fd := Fn / Fm         |
+      | 0 | 1 | 0 | 1 | RDF      | Reverse divide        | Fd := Fm / Fn         |
+      | 0 | 1 | 1 | 0 | POW      | Power                 | Fd := Fn ^ Fm         |
+      | 0 | 1 | 1 | 1 | RPW      | Reverse power         | Fd := Fm ^ Fn         |
+      | 1 | 0 | 0 | 0 | RMF      | Remainder             | Fd := IEEE rem(Fn/Fm) |
+      | 1 | 0 | 0 | 1 | FML      | Fast Multiply         | Fd := Fn * Fm         |
+      | 1 | 0 | 1 | 0 | FDV      | Fast Divide           | Fd := Fn / Fm         |
+      | 1 | 0 | 1 | 1 | FRD      | Fast reverse divide   | Fd := Fm / Fn         |
+      | 1 | 1 | 0 | 0 | POL      | Polar angle (ArcTan2) | Fd := arctan2(Fn,Fm)  |
+      | 1 | 1 | 0 | 1 |          | undefined instruction | trap                  |
+      | 1 | 1 | 1 | 0 |          | undefined instruction | trap                  |
+      | 1 | 1 | 1 | 1 |          | undefined instruction | trap                  |
+      +---+---+---+---+----------+-----------------------+-----------------------+
+      Note: POW, RPW, POL are deprecated, and are available for backwards
+            compatibility only.
+      */
+
+      /*
+      TABLE 4: Monadic Floating Point Opcodes
+      +---+---+---+---+----------+-----------------------+-----------------------+
+      | a | b | c | d | Mnemonic | Description           | Operation             |
+      +---+---+---+---+----------+-----------------------+-----------------------+
+      | 0 | 0 | 0 | 0 | MVF      | Move                  | Fd := Fm              |
+      | 0 | 0 | 0 | 1 | MNF      | Move negated          | Fd := - Fm            |
+      | 0 | 0 | 1 | 0 | ABS      | Absolute value        | Fd := abs(Fm)         |
+      | 0 | 0 | 1 | 1 | RND      | Round to integer      | Fd := int(Fm)         |
+      | 0 | 1 | 0 | 0 | SQT      | Square root           | Fd := sqrt(Fm)        |
+      | 0 | 1 | 0 | 1 | LOG      | Log base 10           | Fd := log10(Fm)       |
+      | 0 | 1 | 1 | 0 | LGN      | Log base e            | Fd := ln(Fm)          |
+      | 0 | 1 | 1 | 1 | EXP      | Exponent              | Fd := e ^ Fm          |
+      | 1 | 0 | 0 | 0 | SIN      | Sine                  | Fd := sin(Fm)         |
+      | 1 | 0 | 0 | 1 | COS      | Cosine                | Fd := cos(Fm)         |
+      | 1 | 0 | 1 | 0 | TAN      | Tangent               | Fd := tan(Fm)         |
+      | 1 | 0 | 1 | 1 | ASN      | Arc Sine              | Fd := arcsin(Fm)      |
+      | 1 | 1 | 0 | 0 | ACS      | Arc Cosine            | Fd := arccos(Fm)      |
+      | 1 | 1 | 0 | 1 | ATN      | Arc Tangent           | Fd := arctan(Fm)      |
+      | 1 | 1 | 1 | 0 | URD      | Unnormalized round    | Fd := int(Fm)         |
+      | 1 | 1 | 1 | 1 | NRM      | Normalize             | Fd := norm(Fm)        |
+      +---+---+---+---+----------+-----------------------+-----------------------+
+      Note: LOG, LGN, EXP, SIN, COS, TAN, ASN, ACS, ATN are deprecated, and are
+            available for backwards compatibility only.
+      */
+
+      /*
+      TABLE 5
+      +-------------------------+---+---+
+      |  Rounding Precision     | e | f |
+      +-------------------------+---+---+
+      | IEEE Single precision   | 0 | 0 |
+      | IEEE Double precision   | 0 | 1 |
+      | IEEE Extended precision | 1 | 0 |
+      | undefined (trap)        | 1 | 1 |
+      +-------------------------+---+---+
+      */
+
+      /*
+      TABLE 5
+      +---------------------------------+---+---+
+      |  Rounding Mode                  | g | h |
+      +---------------------------------+---+---+
+      | Round to nearest (default)      | 0 | 0 |
+      | Round toward plus infinity      | 0 | 1 |
+      | Round toward negative infinity  | 1 | 0 |
+      | Round toward zero               | 1 | 1 |
+      +---------------------------------+---+---+
+*)
+    function taicpu.GetString:string;
+      begin
+        result:='';
+      end;
+
+
     procedure taicpu.ResetPass1;
       begin
         { we need to reset everything here, because the choosen insentry
@@ -657,8 +886,49 @@ implementation
       end;
 
 
-    function  taicpu.FindInsentry:boolean;
+    function taicpu.FindInsentry:boolean;
+      var
+        i : longint;
       begin
+        result:=false;
+      { Things which may only be done once, not when a second pass is done to
+        optimize }
+        if (Insentry=nil) or ((InsEntry^.flags and IF_PASS2)<>0) then
+         begin
+           { create the .ot fields }
+           create_ot;
+           { set the file postion }
+           aktfilepos:=fileinfo;
+         end
+        else
+         begin
+           { we've already an insentry so it's valid }
+           result:=true;
+           exit;
+         end;
+        { Lookup opcode in the table }
+        InsSize:=-1;
+        i:=instabcache^[opcode];
+        if i=-1 then
+         begin
+           Message1(asmw_e_opcode_not_in_table,gas_op2str[opcode]);
+           exit;
+         end;
+        insentry:=@instab[i];
+        while (insentry^.opcode=opcode) do
+         begin
+           if matches(insentry)=100 then
+             begin
+               result:=true;
+               exit;
+             end;
+           inc(i);
+           insentry:=@instab[i];
+         end;
+        Message1(asmw_e_invalid_opcode_and_operands,GetString);
+        { No instruction found, set insentry to nil and inssize to -1 }
+        insentry:=nil;
+        inssize:=-1;
       end;
 
 
@@ -1602,4 +1872,4 @@ static char *CC[] =
 
 *)
 {$endif dummy
-}
+}

compiler/arm/armatt.inc

@@ -1,63 +1,90 @@
 { don't edit, this file is generated from armins.dat }
 (
+'none',
+'abs',
+'acs',
+'asn',
+'atn',
 'adc',
 'add',
+'adf',
 'and',
 'b',
 'bic',
 'bl',
+'blx',
+'bkpt',
 'bx',
 'cdp',
+'cmf',
+'cmfe',
 'cmn',
 'cmp',
-'dcb',
+'clz',
-'dcd',
+'cnf',
-'dcw',
+'cos',
-'dq',
+'dvf',
-'dt',
 'eor',
+'exp',
+'fdv',
+'flt',
+'fix',
+'fml',
+'frd',
 'ldc',
-'ldmda',
+'ldm',
-'ldmdb',
+'ldrbt',
-'ldmea',
+'ldrb',
-'ldmed',
-'ldmfa',
-'ldmfd',
-'ldmia',
-'ldmib',
 'ldr',
 'ldrh',
 'ldrsb',
 'ldrsh',
+'ldrt',
+'ldf',
+'lfm',
+'lgn',
+'log',
 'mcr',
 'mla',
 'mov',
-'mrc',
+'mnf',
-'mrs',
+'muf',
-'msr',
 'mul',
+'mvf',
 'mvn',
 'orr',
+'rdf',
+'rfs',
+'rfc',
+'rmf',
+'rpw',
 'rsb',
 'rsc',
+'rsf',
+'rnd',
+'pol',
 'sbc',
+'sfm',
+'sin',
 'smlal',
 'smull',
-'stmda',
+'sqt',
-'stmdb',
+'suf',
-'stmea',
+'stf',
-'stmed',
+'stm',
-'stmfa',
-'stmfd',
-'stmia',
-'stmib',
 'str',
+'strb',
+'strbt',
 'strh',
+'strt',
 'sub',
 'swi',
 'swp',
+'swpb',
+'tan',
 'teq',
 'tst',
 'umlal',
-'umull'
+'umull',
+'wfs'
 );

compiler/arm/armatts.inc

@@ -59,5 +59,32 @@ attsufNONE,
 attsufNONE,
 attsufNONE,
 attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
+attsufNONE,
 attsufNONE
 );

compiler/arm/armins.dat

@@ -40,6 +40,58 @@
 ; \xE  - reg,reg,<shift>#imm		[-"-]
 ; \xF  - reg,#imm			[-"-]
 ;
+; \xFx - floating point instructions
+;        Floating point instruction format information, taken from the linux kernel,
+;        for detailed tables, see aasmcpu.pas
+;
+;        ARM Floating Point Instruction Classes
+;        | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
+;        |c o n d|1 1 0 P|U|u|W|L|   Rn  |v|  Fd |0|0|0|1|  o f f s e t  | CPDT
+;        |c o n d|1 1 0 P|U|w|W|L|   Rn  |x|  Fd |0|0|1|0|  o f f s e t  | CPDT (copro 2)
+;        | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
+;        |c o n d|1 1 1 0|a|b|c|d|e|  Fn |j|  Fd |0|0|0|1|f|g|h|0|i|  Fm | CPDO
+;        |c o n d|1 1 1 0|a|b|c|L|e|  Fn |   Rd  |0|0|0|1|f|g|h|1|i|  Fm | CPRT
+;        |c o n d|1 1 1 0|a|b|c|1|e|  Fn |1|1|1|1|0|0|0|1|f|g|h|1|i|  Fm | comparisons
+;        | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |
+;
+;        CPDT            data transfer instructions
+;                        LDF, STF, LFM (copro 2), SFM (copro 2)
+;
+;        CPDO            dyadic arithmetic instructions
+;                        ADF, MUF, SUF, RSF, DVF, RDF,
+;                        POW, RPW, RMF, FML, FDV, FRD, POL
+;
+;        CPDO            monadic arithmetic instructions
+;                        MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,
+;                        SIN, COS, TAN, ASN, ACS, ATN, URD, NRM
+;
+;        CPRT            joint arithmetic/data transfer instructions
+;                        FIX (arithmetic followed by load/store)
+;                        FLT (load/store followed by arithmetic)
+;                        CMF, CNF CMFE, CNFE (comparisons)
+;                        WFS, RFS (write/read floating point status register)
+;                        WFC, RFC (write/read floating point control register)
+; \xF0 - CPDT
+;        code 1: copro (1/2)
+;        code 2: load/store bit
+; \xF1 - CPDO
+; \xF2 - CPDO monadic
+; \xF3 - CPRT
+; \xF4 - CPRT comparison
+;
+; \xFF - fix me
+;
+
+[NONE]
+void                  void                            none
+
+[ABScc]
+
+[ACScc]
+
+[ASNcc]
+
+[ATNcc]
 
 [ADCcc]
 reg32,reg32,reg32        \4\x0\xA0                     ARM7
@@ -53,6 +105,8 @@ reg32,reg32,reg32,reg32  \5\x0\x80                     ARM7
 reg32,reg32,reg32,imm    \6\x0\x80                     ARM7
 reg32,reg32,imm          \7\x2\x80                     ARM7
 
+[ADFcc]
+
 [ANDcc]
 reg32,reg32,reg32        \4\x0\x00                     ARM7
 reg32,reg32,reg32,reg32  \5\x0\x00                     ARM7
@@ -73,12 +127,21 @@ reg32,reg32,imm          \7\x3\xC0                     ARM7
 mem32                    \1\x0B                        ARM7
 imm32                    \1\x0B                        ARM7
 
+[BLX]
+mem32                    \xff                        ARM7
+imm32                    \xff                        ARM7
+
+[BKPTcc]
 
 [BXcc]
 reg32                    \3\x01\x2F\xFF\x10            ARM7
 
 [CDP]
-reg8,reg8           \300\1\x10\101                8086
+reg8,reg8           \300\1\x10\101                ARM7
+
+[CMFcc]
+
+[CMFEcc]
 
 [CMNcc]
 reg32,reg32              \xC\x1\x60                     ARM7
@@ -92,20 +155,14 @@ reg32,reg32,reg32        \xD\x1\x40                     ARM7
 reg32,reg32,imm          \xE\x1\x40                     ARM7
 reg32,imm                \xF\x3\x40                     ARM7
 
-[DCB]
+[CLZcc]
-ignore                   ignore                        ignore
+reg32,reg32              \x27\x01\x01                   ARM7
 
-[DCD]
+[CNFcc]
-ignore                   ignore                        ignore
 
-[DCW]
+[COScc]
-ignore                   ignore                        ignore
 
-[DQ]
+[DVFcc]
-ignore                   ignore                        ignore
-
-[DT]
-ignore                   ignore                        ignore
 
 [EORcc]
 reg32,reg32,reg32        \4\x0\x20                     ARM7
@@ -113,32 +170,27 @@ reg32,reg32,reg32,reg32  \5\x0\x20                     ARM7
 reg32,reg32,reg32,imm    \6\x0\x20                     ARM7
 reg32,reg32,imm          \7\x2\x20                     ARM7
 
+[EXPcc]
+
+[FDVcc]
+
+[FLTcc]
+
+[FIXcc]
+
+[FMLcc]
+
+[FRDcc]
+
 [LDC]
 reg32,reg32         \321\300\1\x11\101            ARM7
 
-[LDMDAcc]
+[LDMcc]
 reg32,reglist		   \x26\x81			ARM7
 
-[LDMDBcc]
+[LDRBTcc]
-reg32,reglist		   \x26\x91			ARM7
 
-[LDMEAcc]
+[LDRBcc]
-reg32,reglist		   \x26\x91			ARM7
-
-[LDMEDcc]
-reg32,reglist		   \x26\x99			ARM7
-
-[LDMFAcc]
-reg32,reglist		   \x26\x81			ARM7
-
-[LDMFDcc]
-reg32,reglist		   \x26\x89			ARM7
-
-[LDMIAcc]
-reg32,reglist		   \x26\x89			ARM7
-
-[LDMIBcc]
-reg32,reglist		   \x26\x99			ARM7
 
 [LDRcc]
 reg32,imm32              \x17\x05\x10                   ARM7
@@ -165,8 +217,19 @@ reg32,reg32              \x23\x50\xF0               ARM7
 reg32,reg32,imm32        \x24\x50\xF0                   ARM7
 reg32,reg32,reg32        \x25\x10\xF0                   ARM7
 
+[LDRTcc]
+
+[LDFcc]
+
+[LFMcc]
+reg32,imm8,fpureg        \xF0\x02\x01                   FPA
+
+[LGNcc]
+
+[LOGcc]
+
 [MCR]
-reg32,mem32         \320\301\1\x13\110            8086
+reg32,mem32         \320\301\1\x13\110            ARM7
 
 [MLAcc]
 reg32,reg32,reg32,reg32  \x15\x00\x20\x90               ARM7
@@ -177,20 +240,28 @@ reg32,reg32,reg32        \x9\x1\xA0                     ARM7
 reg32,reg32,imm          \xA\x1\xA0                     ARM7
 reg32,imm                \xB\x3\xA0                     ARM7
 
-[MRC]
+; [MRC]
-reg32,reg32         \321\301\1\x13\110                  ARM7
+; reg32,reg32         \321\301\1\x13\110                  ARM7
 
-[MRScc]
+; [MRScc]
-reg32,reg32         \x10\x01\x0F                        ARM7
+; reg32,reg32         \x10\x01\x0F                        ARM7
 
-[MSRcc]
+; [MSRcc]
-reg32,reg32         \x11\x01\x29\xF0                    ARM7
+; reg32,reg32         \x11\x01\x29\xF0                    ARM7
-regf,reg32          \x12\x01\x28\xF0                    ARM7
+; regf,reg32          \x12\x01\x28\xF0                    ARM7
-regf,imm            \x13\x03\x28\xF0                    ARM7
+; regf,imm            \x13\x03\x28\xF0                    ARM7
+
+[MNFcc]
+
+[MUFcc]
 
 [MULcc]
 reg32,reg32,reg32        \x14\x00\x00\x90          ARM7
 
+[MVFcc]
+fpureg,fpureg              \xF2                      FPA
+fpureg,immfpu              \xF2                      FPA
+
 [MVNcc]
 reg32,reg32         \x8\x1\xE0                     ARM7
 reg32,reg32,reg32   \x9\x1\xE0                     ARM7
@@ -203,6 +274,16 @@ reg32,reg32,reg32,reg32  \5\x1\x80                     ARM7
 reg32,reg32,reg32,imm    \6\x1\x80                     ARM7
 reg32,reg32,imm          \7\x3\x80                     ARM7
 
+[RDFcc]
+
+[RFScc]
+
+[RFCcc]
+
+[RMFcc]
+
+[RPWcc]
+
 [RSBcc]
 reg32,reg32,reg32        \4\x0\x60                     ARM7
 reg32,reg32,reg32,reg32  \5\x0\x60                     ARM7
@@ -215,42 +296,38 @@ reg32,reg32,reg32,reg32  \5\x0\xE0                     ARM7
 reg32,reg32,reg32,imm    \6\x0\xE0                     ARM7
 reg32,reg32,imm          \7\x2\xE0                     ARM7
 
+[RSFcc]
+
+[RNDcc]
+
+[POLcc]
+
 [SBCcc]
 reg32,reg32,reg32        \4\x0\xC0                     ARM7
 reg32,reg32,reg32,reg32  \5\x0\xC0                     ARM7
 reg32,reg32,reg32,imm    \6\x0\xC0                     ARM7
 reg32,reg32,imm          \7\x2\xC0                     ARM7
 
+[SFMcc]
+reg32,imm8,fpureg        \xF0\x02\x00                   FPA
+
+[SINcc]
+
 [SMLALcc]
 reg32,reg32,reg32,reg32  \x16\x00\xE0\x90		 ARM7
 
 [SMULLcc]
 reg32,reg32,reg32,reg32  \x16\x00\xC0\x90		 ARM7
 
-[STMDAcc]
+[SQTcc]
+
+[SUFcc]
+
+[STFcc]
+
+[STMcc]
 reg32,reglist		   \x26\x80			ARM7
 
-[STMDBcc]
-reg32,reglist		   \x26\x90			ARM7
-
-[STMEAcc]
-reg32,reglist		   \x26\x88			ARM7
-
-[STMEDcc]	  
-reg32,reglist		   \x26\x80			ARM7
-
-[STMFAcc]
-reg32,reglist		   \x26\x98			ARM7
-
-[STMFDcc]
-reg32,reglist		   \x26\x90			ARM7
-
-[STMIAcc]
-reg32,reglist		   \x26\x88			ARM7
-
-[STMIBcc]
-reg32,reglist		   \x26\x98			ARM7
-
 [STRcc]
 reg32,imm32              \x17\x05\x00                   ARM7
 reg32,reg32              \x18\x04\x00                   ARM7
@@ -258,6 +335,10 @@ reg32,reg32,imm32        \x19\x04\x00                   ARM7
 reg32,reg32,reg32        \x20\x06\x00                   ARM7
 reg32,reg32,reg32,imm32  \x21\x06\x00                   ARM7
 
+[STRBcc]
+
+[STRBTcc]
+
 ; A dummy since it is parsed as STR{cond}H
 [STRHcc]
 reg32,imm32              \x22\x40\xB0              ARM7
@@ -265,6 +346,8 @@ reg32,reg32              \x23\x40\xB0               ARM7
 reg32,reg32,imm32        \x24\x40\xB0                   ARM7
 reg32,reg32,reg32        \x25\x00\xB0                   ARM7
 
+[STRTcc]
+
 [SUBcc]
 reg32,reg32,reg32        \4\x0\x40                     ARM7
 reg32,reg32,reg32,reg32  \5\x0\x40                     ARM7
@@ -272,11 +355,16 @@ reg32,reg32,reg32,imm    \6\x0\x40                     ARM7
 reg32,reg32,imm          \7\x2\x40                     ARM7
 
 [SWIcc]
-imm                 \2\x0F                        8086
+imm                 \2\x0F                        ARM7
 
 [SWPcc]
 reg32,reg32,reg32   \x27\x01\x90                   ARM7
 
+[SWPBcc]
+reg32,reg32,reg32   \x27\x01\x90                   ARM7
+
+[TANcc]
+
 [TEQcc]
 reg32,reg32         \xC\x1\x20                     ARM7
 reg32,reg32,reg32   \xD\x1\x20                     ARM7
@@ -291,5 +379,9 @@ reg32,imm           \xF\x3\x00                     ARM7
 
 [UMLALcc]
 reg32,reg32,reg32,reg32  \x16\x00\xA0\x90		 ARM7
+
 [UMULLcc]
 reg32,reg32,reg32,reg32  \x16\x00\x80\x90		 ARM7
+
+[WFScc]
+

compiler/arm/armnop.inc

@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armins.dat }
-132;
+117;

compiler/arm/armop.inc

@@ -1,63 +1,90 @@
 { don't edit, this file is generated from armins.dat }
 (
+A_NONE,
+A_ABS,
+A_ACS,
+A_ASN,
+A_ATN,
 A_ADC,
 A_ADD,
+A_ADF,
 A_AND,
 A_B,
 A_BIC,
 A_BL,
+A_BLX,
+A_BKPT,
 A_BX,
 A_CDP,
+A_CMF,
+A_CMFE,
 A_CMN,
 A_CMP,
-A_DCB,
+A_CLZ,
-A_DCD,
+A_CNF,
-A_DCW,
+A_COS,
-A_DQ,
+A_DVF,
-A_DT,
 A_EOR,
+A_EXP,
+A_FDV,
+A_FLT,
+A_FIX,
+A_FML,
+A_FRD,
 A_LDC,
-A_LDMDA,
+A_LDM,
-A_LDMDB,
+A_LDRBT,
-A_LDMEA,
+A_LDRB,
-A_LDMED,
-A_LDMFA,
-A_LDMFD,
-A_LDMIA,
-A_LDMIB,
 A_LDR,
 A_LDRH,
 A_LDRSB,
 A_LDRSH,
+A_LDRT,
+A_LDF,
+A_LFM,
+A_LGN,
+A_LOG,
 A_MCR,
 A_MLA,
 A_MOV,
-A_MRC,
+A_MNF,
-A_MRS,
+A_MUF,
-A_MSR,
 A_MUL,
+A_MVF,
 A_MVN,
 A_ORR,
+A_RDF,
+A_RFS,
+A_RFC,
+A_RMF,
+A_RPW,
 A_RSB,
 A_RSC,
+A_RSF,
+A_RND,
+A_POL,
 A_SBC,
+A_SFM,
+A_SIN,
 A_SMLAL,
 A_SMULL,
-A_STMDA,
+A_SQT,
-A_STMDB,
+A_SUF,
-A_STMEA,
+A_STF,
-A_STMED,
+A_STM,
-A_STMFA,
-A_STMFD,
-A_STMIA,
-A_STMIB,
 A_STR,
+A_STRB,
+A_STRBT,
 A_STRH,
+A_STRT,
 A_SUB,
 A_SWI,
 A_SWP,
+A_SWPB,
+A_TAN,
 A_TEQ,
 A_TST,
 A_UMLAL,
-A_UMULL
+A_UMULL,
+A_WFS
 );

compiler/arm/armtab.inc

@@ -1,9 +1,16 @@
 { don't edit, this file is generated from armins.dat }
 (
+  (
+    opcode  : A_NONE;
+    ops     : 0;
+    optypes : (ot_none,ot_none,ot_none,ot_none);
+    code    : #0;
+    flags   : if_none
+  ),
   (
     opcode  : A_ADC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#0#160;
     flags   : if_arm7
   ),
@@ -24,14 +31,14 @@
   (
     opcode  : A_ADC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#2#160;
     flags   : if_arm7
   ),
   (
     opcode  : A_ADD;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#0#128;
     flags   : if_arm7
   ),
@@ -52,14 +59,14 @@
   (
     opcode  : A_ADD;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#2#128;
     flags   : if_arm7
   ),
   (
     opcode  : A_AND;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#0#0;
     flags   : if_arm7
   ),
@@ -80,28 +87,28 @@
   (
     opcode  : A_AND;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#2#0;
     flags   : if_arm7
   ),
   (
     opcode  : A_B;
     ops     : 1;
-    optypes : (ot_memory or ot_bits32,ot_none,ot_none,);
+    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none);
     code    : #1#10;
     flags   : if_arm7
   ),
   (
     opcode  : A_B;
     ops     : 1;
-    optypes : (ot_immediate or ot_bits32,ot_none,ot_none,);
+    optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none);
     code    : #1#10;
     flags   : if_arm7
   ),
   (
     opcode  : A_BIC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#1#192;
     flags   : if_arm7
   ),
@@ -122,133 +129,119 @@
   (
     opcode  : A_BIC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#3#192;
     flags   : if_arm7
   ),
   (
     opcode  : A_BL;
     ops     : 1;
-    optypes : (ot_memory or ot_bits32,ot_none,ot_none,);
+    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none);
     code    : #1#11;
     flags   : if_arm7
   ),
   (
     opcode  : A_BL;
     ops     : 1;
-    optypes : (ot_immediate or ot_bits32,ot_none,ot_none,);
+    optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none);
     code    : #1#11;
     flags   : if_arm7
   ),
+  (
+    opcode  : A_BLX;
+    ops     : 1;
+    optypes : (ot_memory or ot_bits32,ot_none,ot_none,ot_none);
+    code    : #15#15;
+    flags   : if_arm7
+  ),
+  (
+    opcode  : A_BLX;
+    ops     : 1;
+    optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none);
+    code    : #15#15;
+    flags   : if_arm7
+  ),
   (
     opcode  : A_BX;
     ops     : 1;
-    optypes : (ot_reg32,ot_none,ot_none,);
+    optypes : (ot_reg32,ot_none,ot_none,ot_none);
     code    : #3#1#47#255#16;
     flags   : if_arm7
   ),
   (
     opcode  : A_CDP;
     ops     : 2;
-    optypes : (ot_reg8,ot_reg8,ot_none,);
+    optypes : (ot_reg8,ot_reg8,ot_none,ot_none);
     code    : #192#1#16#65;
-    flags   : if_8086
+    flags   : if_arm7
   ),
   (
     opcode  : A_CMN;
     ops     : 2;
-    optypes : (ot_reg32 or ot_signed,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #12#1#96;
     flags   : if_arm7
   ),
   (
     opcode  : A_CMN;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32 or ot_signed,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #13#1#96;
     flags   : if_arm7
   ),
   (
     opcode  : A_CMN;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_signed,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #14#1#96;
     flags   : if_arm7
   ),
   (
     opcode  : A_CMN;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,);
+    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
     code    : #15#3#96;
     flags   : if_arm7
   ),
   (
     opcode  : A_CMP;
     ops     : 2;
-    optypes : (ot_reg32 or ot_signed,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #12#1#64;
     flags   : if_arm7
   ),
   (
     opcode  : A_CMP;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32 or ot_signed,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #13#1#64;
     flags   : if_arm7
   ),
   (
     opcode  : A_CMP;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_signed,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #14#1#64;
     flags   : if_arm7
   ),
   (
     opcode  : A_CMP;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,);
+    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
     code    : #15#3#64;
     flags   : if_arm7
   ),
   (
-    opcode  : A_DCB;
+    opcode  : A_CLZ;
-    ops     : 0;
+    ops     : 2;
-    optypes : (ot_none,ot_none,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
-    code    : #0;
+    code    : #39#1#1;
-    flags   : if_ignore
+    flags   : if_arm7
-  ),
-  (
-    opcode  : A_DCD;
-    ops     : 0;
-    optypes : (ot_none,ot_none,ot_none,);
-    code    : #0;
-    flags   : if_ignore
-  ),
-  (
-    opcode  : A_DCW;
-    ops     : 0;
-    optypes : (ot_none,ot_none,ot_none,);
-    code    : #0;
-    flags   : if_ignore
-  ),
-  (
-    opcode  : A_DQ;
-    ops     : 0;
-    optypes : (ot_none,ot_none,ot_none,);
-    code    : #0;
-    flags   : if_ignore
-  ),
-  (
-    opcode  : A_DT;
-    ops     : 0;
-    optypes : (ot_none,ot_none,ot_none,);
-    code    : #0;
-    flags   : if_ignore
   ),
   (
     opcode  : A_EOR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#0#32;
     flags   : if_arm7
   ),
@@ -269,98 +262,49 @@
   (
     opcode  : A_EOR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#2#32;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDC;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #209#192#1#17#65;
     flags   : if_arm7
   ),
   (
-    opcode  : A_LDMDA;
+    opcode  : A_LDM;
     ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
+    optypes : (ot_reg32,ot_reglist,ot_none,ot_none);
     code    : #38#129;
     flags   : if_arm7
   ),
-  (
-    opcode  : A_LDMDB;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#145;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_LDMEA;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#145;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_LDMED;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#153;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_LDMFA;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#129;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_LDMFD;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#137;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_LDMIA;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#137;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_LDMIB;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#153;
-    flags   : if_arm7
-  ),
   (
     opcode  : A_LDR;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,);
+    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
     code    : #23#5#16;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDR;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #24#4#16;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
     code    : #25#4#16;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #32#6#16;
     flags   : if_arm7
   ),
@@ -374,93 +318,100 @@
   (
     opcode  : A_LDRH;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,);
+    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
     code    : #34#80#176;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRH;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #35#80#176;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRH;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
     code    : #36#80#176;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRH;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #37#16#176;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRSB;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,);
+    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
     code    : #34#80#208;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRSB;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #35#80#208;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRSB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
     code    : #36#80#208;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRSB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #37#16#208;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRSH;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,);
+    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
     code    : #34#80#240;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRSH;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #35#80#240;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRSH;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
     code    : #36#80#240;
     flags   : if_arm7
   ),
   (
     opcode  : A_LDRSH;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #37#16#240;
     flags   : if_arm7
   ),
+  (
+    opcode  : A_LFM;
+    ops     : 3;
+    optypes : (ot_reg32,ot_immediate or ot_bits8,ot_fpureg,ot_none);
+    code    : #240#2#1;
+    flags   : if_fpa
+  ),
   (
     opcode  : A_MCR;
     ops     : 2;
-    optypes : (ot_reg32,ot_memory or ot_bits32,ot_none,);
+    optypes : (ot_reg32,ot_memory or ot_bits32,ot_none,ot_none);
     code    : #208#193#1#19#72;
-    flags   : if_8086
+    flags   : if_arm7
   ),
   (
     opcode  : A_MLA;
@@ -472,105 +423,84 @@
   (
     opcode  : A_MOV;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #8#1#160;
     flags   : if_arm7
   ),
   (
     opcode  : A_MOV;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #9#1#160;
     flags   : if_arm7
   ),
   (
     opcode  : A_MOV;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #10#1#160;
     flags   : if_arm7
   ),
   (
     opcode  : A_MOV;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,);
+    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
     code    : #11#3#160;
     flags   : if_arm7
   ),
-  (
-    opcode  : A_MRC;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
-    code    : #209#193#1#19#72;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_MRS;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
-    code    : #16#1#15;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_MSR;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
-    code    : #17#1#41#240;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_MSR;
-    ops     : 2;
-    optypes : (ot_regf,ot_reg32,ot_none,);
-    code    : #18#1#40#240;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_MSR;
-    ops     : 2;
-    optypes : (ot_regf,ot_immediate,ot_none,);
-    code    : #19#3#40#240;
-    flags   : if_arm7
-  ),
   (
     opcode  : A_MUL;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #20#0#0#144;
     flags   : if_arm7
   ),
+  (
+    opcode  : A_MVF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none);
+    code    : #242;
+    flags   : if_fpa
+  ),
+  (
+    opcode  : A_MVF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediatefpu,ot_none,ot_none);
+    code    : #242;
+    flags   : if_fpa
+  ),
   (
     opcode  : A_MVN;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #8#1#224;
     flags   : if_arm7
   ),
   (
     opcode  : A_MVN;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #9#1#224;
     flags   : if_arm7
   ),
   (
     opcode  : A_MVN;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #10#1#224;
     flags   : if_arm7
   ),
   (
     opcode  : A_MVN;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,);
+    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
     code    : #11#3#224;
     flags   : if_arm7
   ),
   (
     opcode  : A_ORR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#1#128;
     flags   : if_arm7
   ),
@@ -591,14 +521,14 @@
   (
     opcode  : A_ORR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#3#128;
     flags   : if_arm7
   ),
   (
     opcode  : A_RSB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#0#96;
     flags   : if_arm7
   ),
@@ -619,14 +549,14 @@
   (
     opcode  : A_RSB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#2#96;
     flags   : if_arm7
   ),
   (
     opcode  : A_RSC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#0#224;
     flags   : if_arm7
   ),
@@ -647,14 +577,14 @@
   (
     opcode  : A_RSC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#2#224;
     flags   : if_arm7
   ),
   (
     opcode  : A_SBC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#0#192;
     flags   : if_arm7
   ),
@@ -675,10 +605,17 @@
   (
     opcode  : A_SBC;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#2#192;
     flags   : if_arm7
   ),
+  (
+    opcode  : A_SFM;
+    ops     : 3;
+    optypes : (ot_reg32,ot_immediate or ot_bits8,ot_fpureg,ot_none);
+    code    : #240#2#0;
+    flags   : if_fpa
+  ),
   (
     opcode  : A_SMLAL;
     ops     : 4;
@@ -694,86 +631,37 @@
     flags   : if_arm7
   ),
   (
-    opcode  : A_STMDA;
+    opcode  : A_STM;
     ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
+    optypes : (ot_reg32,ot_reglist,ot_none,ot_none);
     code    : #38#128;
     flags   : if_arm7
   ),
-  (
-    opcode  : A_STMDB;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#144;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_STMEA;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#136;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_STMED;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#128;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_STMFA;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#152;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_STMFD;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#144;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_STMIA;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#136;
-    flags   : if_arm7
-  ),
-  (
-    opcode  : A_STMIB;
-    ops     : 2;
-    optypes : (ot_reg32,ot_reglist,ot_none,);
-    code    : #38#152;
-    flags   : if_arm7
-  ),
   (
     opcode  : A_STR;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,);
+    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
     code    : #23#5#0;
     flags   : if_arm7
   ),
   (
     opcode  : A_STR;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #24#4#0;
     flags   : if_arm7
   ),
   (
     opcode  : A_STR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
     code    : #25#4#0;
     flags   : if_arm7
   ),
   (
     opcode  : A_STR;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #32#6#0;
     flags   : if_arm7
   ),
@@ -787,35 +675,35 @@
   (
     opcode  : A_STRH;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,);
+    optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
     code    : #34#64#176;
     flags   : if_arm7
   ),
   (
     opcode  : A_STRH;
     ops     : 2;
-    optypes : (ot_reg32,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #35#64#176;
     flags   : if_arm7
   ),
   (
     opcode  : A_STRH;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
     code    : #36#64#176;
     flags   : if_arm7
   ),
   (
     opcode  : A_STRH;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #37#0#176;
     flags   : if_arm7
   ),
   (
     opcode  : A_SUB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #4#0#64;
     flags   : if_arm7
   ),
@@ -836,77 +724,84 @@
   (
     opcode  : A_SUB;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #7#2#64;
     flags   : if_arm7
   ),
   (
     opcode  : A_SWI;
     ops     : 1;
-    optypes : (ot_immediate,ot_none,ot_none,);
+    optypes : (ot_immediate,ot_none,ot_none,ot_none);
     code    : #2#15;
-    flags   : if_8086
+    flags   : if_arm7
   ),
   (
     opcode  : A_SWP;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
+    code    : #39#1#144;
+    flags   : if_arm7
+  ),
+  (
+    opcode  : A_SWPB;
+    ops     : 3;
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #39#1#144;
     flags   : if_arm7
   ),
   (
     opcode  : A_TEQ;
     ops     : 2;
-    optypes : (ot_reg32 or ot_signed,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #12#1#32;
     flags   : if_arm7
   ),
   (
     opcode  : A_TEQ;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32 or ot_signed,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #13#1#32;
     flags   : if_arm7
   ),
   (
     opcode  : A_TEQ;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_signed,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #14#1#32;
     flags   : if_arm7
   ),
   (
     opcode  : A_TEQ;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,);
+    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
     code    : #15#3#32;
     flags   : if_arm7
   ),
   (
     opcode  : A_TST;
     ops     : 2;
-    optypes : (ot_reg32 or ot_signed,ot_reg32,ot_none,);
+    optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
     code    : #12#1#0;
     flags   : if_arm7
   ),
   (
     opcode  : A_TST;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32 or ot_signed,ot_reg32,);
+    optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
     code    : #13#1#0;
     flags   : if_arm7
   ),
   (
     opcode  : A_TST;
     ops     : 3;
-    optypes : (ot_reg32,ot_reg32,ot_immediate or ot_signed,);
+    optypes : (ot_reg32,ot_reg32,ot_immediate,ot_none);
     code    : #14#1#0;
     flags   : if_arm7
   ),
   (
     opcode  : A_TST;
     ops     : 2;
-    optypes : (ot_reg32,ot_immediate,ot_none,);
+    optypes : (ot_reg32,ot_immediate,ot_none,ot_none);
     code    : #15#3#0;
     flags   : if_arm7
   ),

compiler/arm/cpubase.pas

@@ -43,24 +43,7 @@ unit cpubase;
 *****************************************************************************}
 
     type
-      TAsmOp=(A_None,A_ADC,A_ADD,A_AND,A_N,A_BIC,A_BKPT,A_B,A_BL,A_BLX,A_BX,
+      TAsmOp= {$i armop.inc}
-              A_CDP,A_CDP2,A_CLZ,A_CMN,A_CMP,A_EOR,A_LDC,_A_LDC2,
-              A_LDM,A_LDR,A_LDRB,A_LDRD,A_LDRBT,A_LDRH,A_LDRSB,
-              A_LDRSH,A_LDRT,A_MCR,A_MCR2,A_MCRR,A_MLA,A_MOV,
-              A_MRC,A_MRC2,A_MRRC,A_RS,A_MSR,A_MUL,A_MVN,
-              A_ORR,A_PLD,A_QADD,A_QDADD,A_QDSUB,A_QSUB,A_RSB,A_RSC,
-              A_SBC,A_SMLAL,A_SMULL,A_SMUL,
-              A_SMULW,A_STC,A_STC2,A_STM,A_STR,A_STRB,A_STRBT,A_STRD,
-              A_STRH,A_STRT,A_SUB,A_SWI,A_SWP,A_SWPB,A_TEQ,A_TST,
-              A_UMLAL,A_UMULL,
-              { FPA coprocessor instructions }
-              A_LDF,A_STF,A_LFM,A_SFM,A_FLT,A_FIX,A_WFS,A_RFS,A_RFC,
-              A_ADF,A_DVF,A_FDV,A_FML,A_FRD,A_MUF,A_POL,A_PW,A_RDF,
-              A_RMF,A_RPW,A_RSF,A_SUF,A_ABS,A_ACS,A_ASN,A_ATN,A_COS,
-              A_EXP,A_LOG,A_LGN,A_MVF,A_MNF,A_NRM,A_RND,A_SIN,A_SQT,A_TAN,A_URD,
-              A_CMF,A_CMFE,A_CNF
-              { VPA coprocessor codes }
-              );
 
       { This should define the array of instructions as string }
       op2strtable=array[tasmop] of string[11];

compiler/arm/itcpugas.pas

@@ -34,26 +34,7 @@ interface
       opcode strings should conform to the names as defined by the
       processor manufacturer.
     }
-    gas_op2str : op2strtable = (
+    gas_op2str : op2strtable = {$i armatt.inc}
-            '','adc','add','and','n','bic','bkpt','b','bl','blx','bx',
-            'cdp','cdp2','clz','cmn','cmp','eor','ldc','ldc2',
-            'ldm','ldr','ldrb','ldrd','ldrbt','ldrh','ldrsb',
-            'ldrsh','ldrt','mcr','mcr2','mcrr','mla','mov',
-            'mrc','mrc2','mrrc','rs','msr','mul','mvn',
-            'orr','pld','qadd','qdadd','qdsub','qsub','rsb','rsc',
-            'sbc','smlal','smull','smul',
-            'smulw','stc','stc2','stm','str','strb','strbt','strd',
-            'strh','strt','sub','swi','swp','swpb','teq','tst',
-            'umlal','umull',
-            { FPA coprocessor codes }
-            'ldf','stf','lfm','sfm','flt','fix','wfs','rfs','rfc',
-            'adf','dvf','fdv','fml','frd','muf','pol','pw','rdf',
-            'rmf','rpw','rsf','suf','abs','acs','asn','atn','cos',
-            'exp','log','lgn','mvf','mnf','nrm','rnd','sin','sqt','tan','urd',
-            'cmf','cmfe','cnf'
-            { VPA coprocessor codes }
-            );
-
 
     function gas_regnum_search(const s:string):Tregister;
     function gas_regname(r:Tregister):string;

compiler/utils/mkarmins.pp

@@ -352,8 +352,8 @@ begin
           else
             break;
         until false;
-        for j:=1 to 3-ops do
+        for j:=1 to 4-ops do
-          optypes[3-j+1]:='ot_none';
+          optypes[4-j+1]:='ot_none';
         { codes }
         skipspace;
         j:=0;
@@ -363,6 +363,7 @@ begin
              while not(s[i] in [' ',#9]) do
                begin
                  code:=readnumber;
+(*
                  { for some codes we want also to change the optypes, but not
                    if the last byte was a 1 then this byte belongs to a direct
                    copy }
@@ -373,6 +374,7 @@ begin
                         optypes[code-11]:=optypes[code-11]+' or ot_signed';
                     end;
                   end;
+*)
                  codes:=codes+'#'+tostr(code);
                  last:=code;
                  inc(j);