paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-09-22 06:09:14 +02:00
Code Issues Packages Projects Releases Wiki Activity

+ RiscV: support ZMMUL extension

Browse Source
This commit is contained in:
florian 2025-01-26 14:43:57 +01:00
parent cd76562339
commit 95c2a5a2d7
6 changed files with 12 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
compiler/riscv/cgrv.pas
View File

@ -316,7 +316,7 @@ unit cgrv;
end
else
{$endif RISCV64}
if (op in [OP_IMUL,OP_MUL]) and not(CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype]) then
if (op in [OP_IMUL,OP_MUL]) and ([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]=[]) then
begin
case size of
OS_8:

6
compiler/riscv/nrvadd.pas
View File

@ -213,7 +213,7 @@ implementation
function trvaddnode.use_mul_helper: boolean;
begin
if (nodetype=muln) and not(CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype]) then
if (nodetype=muln) and ([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]=[]) then
result:=true
else
Result:=inherited use_mul_helper;
@ -279,7 +279,7 @@ implementation
begin
if (nodetype=muln) and
(left.resultdef.typ=orddef) and (left.resultdef.typ=orddef) and
(CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype])
([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]<>[])
{$ifdef cpu32bitalu}
and (not (is_64bit(left.resultdef) or
is_64bit(right.resultdef)))
@ -294,7 +294,7 @@ implementation
expectloc:=LOC_REGISTER;
end
else if (nodetype=muln) and
(not (CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype])) and
([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]=[]) and
(is_64bit(left.resultdef) or
is_64bit(right.resultdef)) then
begin

2
compiler/riscv/nrvutil.pas
View File

@ -87,6 +87,8 @@ implementation
attr_arch:=attr_arch+'_zicrs2p0';
if CPURV_HAS_FETCH_FENCE in cpu_capabilities[current_settings.cputype] then
attr_arch:=attr_arch+'_zifencei2p0';
if CPURV_HAS_ZMMUL in cpu_capabilities[current_settings.cputype] then
attr_arch:=attr_arch+'_zmmul1p0';
if CPURV_HAS_ZFA in cpu_capabilities[current_settings.cputype] then
attr_arch:=attr_arch+'_zfa1p0';
if CPURV_HAS_ZBA in cpu_capabilities[current_settings.cputype] then

3
compiler/riscv32/cpuinfo.pas
View File

@ -225,7 +225,8 @@ Const
CPURV_HAS_ZDINX,
CPURV_HAS_ZHINX,
CPURV_HAS_ZHINXMIN,
CPURV_HAS_ZICOND
CPURV_HAS_ZICOND,
CPURV_HAS_ZMMUL
);
const

3
compiler/riscv64/cpuinfo.pas
View File

@ -143,7 +143,8 @@ Const
CPURV_HAS_ZDINX,
CPURV_HAS_ZHINX,
CPURV_HAS_ZHINXMIN,
CPURV_HAS_ZICOND
CPURV_HAS_ZICOND,
CPURV_HAS_ZMMUL
);
const

4
compiler/riscv64/nrv64add.pas
View File

@ -57,7 +57,7 @@ unit nrv64add;
begin
if (nodetype=muln) and
(left.resultdef.typ=orddef) and (left.resultdef.typ=orddef) and
(CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype]) then
([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]<>[]) then
begin
result:=nil;
@ -67,7 +67,7 @@ unit nrv64add;
expectloc:=LOC_REGISTER;
end
else if (nodetype=muln) and
(not (CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype])) and
([CPURV_HAS_MUL,CPURV_HAS_ZMMUL]*cpu_capabilities[current_settings.cputype]=[]) and
(is_64bit(left.resultdef) or
is_64bit(right.resultdef)) then
begin