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* basic operand matching works
+ skeleton for pass 2 implemented git-svn-id: trunk@1075 -
This commit is contained in:
florian
parent
6ad3930a5d
commit
95dc2eba5f
@ -102,6 +102,8 @@ uses
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OT_AM5 = $00080000;
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OT_AMMASK = $000f0000;
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OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
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OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
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OT_MEMORYAM4 = OT_MEMORY or OT_AM4;
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OT_MEMORYAM5 = OT_MEMORY or OT_AM5;
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@ -960,6 +962,8 @@ implementation
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internalerror(2005091001);
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if opcode=A_None then
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internalerror(2005091004);
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{ postfix has been added to opcode }
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oppostfix:=PF_None;
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end
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else if (opcode=A_STR) and (oppostfix<>PF_None) then
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begin
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@ -969,6 +973,8 @@ implementation
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internalerror(2005091002);
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if opcode=A_None then
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internalerror(2005091003);
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{ postfix has been added to opcode }
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oppostfix:=PF_None;
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end;
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{ Get InsEntry }
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@ -985,6 +991,12 @@ implementation
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procedure taicpu.Pass2(objdata:TAsmObjectdata);
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begin
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{ error in pass1 ? }
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if insentry=nil then
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exit;
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aktfilepos:=fileinfo;
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{ Generate the instruction }
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GenCode(objdata);
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end;
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@ -1055,6 +1067,16 @@ implementation
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ot:=ot or OT_MEM_OFFS;
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{ if we need to fix a reference, we do it here }
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{ pc relative addressing }
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if (ref^.base=NR_NO) and
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(ref^.index=NR_NO) and
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(ref^.shiftmode=SM_None)
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{ at least we should check if the destination symbol
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is in a text section }
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{ and
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(ref^.symbol^.owner="text") } then
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ref^.base:=NR_PC;
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{ determine possible address modes }
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if (ref^.base<>NR_NO) and
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(
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@ -1201,7 +1223,7 @@ implementation
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{ update condition flags
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or floating point single }
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if (oppostfix=PF_S) and
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not(p^.code[0] in []) then
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not(p^.code[0] in [#$04]) then
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begin
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Matches:=0;
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exit;
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@ -1218,6 +1240,8 @@ implementation
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{ multiple load/store address modes }
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if (oppostfix in [PF_IA,PF_IB,PF_DA,PF_DB,PF_FD,PF_FA,PF_ED,PF_EA]) and
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not(p^.code[0] in [
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// ldr,str,ldrb,strb
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#$17,
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// stm,ldm
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#$26
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]) then
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@ -1308,11 +1332,7 @@ implementation
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function taicpu.calcsize(p:PInsEntry):shortint;
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begin
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end;
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procedure taicpu.gencode(objdata:TAsmObjectData);
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begin
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result:=4;
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end;
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@ -1371,6 +1391,72 @@ implementation
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inssize:=-1;
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end;
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procedure taicpu.gencode(objdata:TAsmObjectData);
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var
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bytes : dword;
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i_field : byte;
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procedure setshifterop(op : byte);
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begin
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case oper[op]^.typ of
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top_const:
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begin
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i_field:=1;
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bytes:=bytes or (oper[op]^.val and $fff);
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end;
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top_reg:
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begin
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i_field:=0;
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bytes:=bytes or (getsupreg(oper[op]^.reg) shl 16);
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{ does a real shifter op follow? }
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if (op+1<=op) and (oper[op+1]^.typ=top_shifterop) then
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begin
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end;
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end;
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else
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internalerror(2005091103);
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end;
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end;
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begin
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bytes:=$0;
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{ evaluate and set condition code }
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{ condition code allowed? }
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{ setup rest of the instruction }
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case insentry^.code[0] of
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#$08:
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begin
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{ set instruction code }
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bytes:=bytes or (ord(insentry^.code[1]) shl 26);
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bytes:=bytes or (ord(insentry^.code[2]) shl 21);
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{ set destination }
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bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
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{ create shifter op }
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setshifterop(1);
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{ set i field }
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bytes:=bytes or (i_field shl 25);
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{ set s if necessary }
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if oppostfix=PF_S then
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bytes:=bytes or (1 shl 20);
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end;
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#$ff:
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internalerror(2005091101);
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else
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internalerror(2005091102);
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end;
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{ we're finished, write code }
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objdata.writebytes(bytes,sizeof(bytes));
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end;
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end.
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{$ifdef dummy}
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@ -115,7 +115,7 @@ reg32,reg32,imm \7\x2\x00 ARM7
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[Bcc]
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mem32 \1\x0A ARM7
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imm32 \1\x0A ARM7
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imm24 \1\x0A ARM7
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[BICcc]
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reg32,reg32,reg32 \4\x1\xC0 ARM7
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@ -191,13 +191,15 @@ memam4,reglist \x26\x81 ARM7
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[LDRBTcc]
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[LDRBcc]
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reg32,memam2 \x17\x07\x10 ARM7
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[LDRcc]
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reg32,imm32 \x17\x05\x10 ARM7
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reg32,reg32 \x18\x04\x10 ARM7
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reg32,reg32,imm32 \x19\x04\x10 ARM7
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reg32,reg32,reg32 \x20\x06\x10 ARM7
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reg32,reg32,reg32,imm32 \x21\x06\x10 ARM7
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reg32,memam2 \x17\x05\x10 ARM7
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; reg32,imm32 \x17\x05\x10 ARM7
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; reg32,reg32 \x18\x04\x10 ARM7
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; reg32,reg32,imm32 \x19\x04\x10 ARM7
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; reg32,reg32,reg32 \x20\x06\x10 ARM7
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; reg32,reg32,reg32,imm32 \x21\x06\x10 ARM7
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[LDRHcc]
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reg32,imm32 \x22\x50\xB0 ARM7
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@ -235,7 +237,8 @@ reg32,mem32 \320\301\1\x13\110 ARM7
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reg32,reg32,reg32,reg32 \x15\x00\x20\x90 ARM7
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[MOVcc]
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reg32,shifterop \x8\x1\xA0 ARM7
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reg32,shifterop \x8\x0\0xd ARM7
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reg32,immshifter \x8\x0\0xd ARM7
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; reg32,reg32,reg32 \x9\x1\xA0 ARM7
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; reg32,reg32,imm \xA\x1\xA0 ARM7
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; reg32,imm \xB\x3\xA0 ARM7
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@ -263,7 +266,7 @@ fpureg,fpureg \xF2 FPA
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fpureg,immfpu \xF2 FPA
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[MVNcc]
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reg32,reg32 \x8\x1\xE0 ARM7
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reg32,reg32 \x8\x0\0xf ARM7
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reg32,reg32,reg32 \x9\x1\xE0 ARM7
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reg32,reg32,imm \xA\x1\xE0 ARM7
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reg32,imm \xB\x3\xE0 ARM7
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@ -329,13 +332,15 @@ reg32,reg32,reg32,reg32 \x16\x00\xC0\x90 ARM7
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memam4,reglist \x26\x80 ARM7
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[STRcc]
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reg32,imm32 \x17\x05\x00 ARM7
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reg32,reg32 \x18\x04\x00 ARM7
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reg32,reg32,imm32 \x19\x04\x00 ARM7
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reg32,reg32,reg32 \x20\x06\x00 ARM7
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reg32,reg32,reg32,imm32 \x21\x06\x00 ARM7
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reg32,memam2 \x17\x04\x00 ARM7
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; reg32,imm32 \x17\x05\x00 ARM7
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; reg32,reg32 \x18\x04\x00 ARM7
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; reg32,reg32,imm32 \x19\x04\x00 ARM7
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; reg32,reg32,reg32 \x20\x06\x00 ARM7
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; reg32,reg32,reg32,imm32 \x21\x06\x00 ARM7
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[STRBcc]
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reg32,memam2 \x17\x06\x00 ARM7
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[STRBTcc]
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@ -1,2 +1,2 @@
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{ don't edit, this file is generated from armins.dat }
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113;
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108;
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@ -101,7 +101,7 @@
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(
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opcode : A_B;
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ops : 1;
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optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none);
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optypes : (ot_immediate24,ot_none,ot_none,ot_none);
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code : #1#10;
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flags : if_arm7
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),
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@ -280,41 +280,20 @@
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code : #38#129;
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flags : if_arm7
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),
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(
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opcode : A_LDRB;
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ops : 2;
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optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
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code : #23#7#16;
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flags : if_arm7
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),
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(
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opcode : A_LDR;
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ops : 2;
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optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
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optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
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code : #23#5#16;
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flags : if_arm7
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),
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(
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opcode : A_LDR;
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ops : 2;
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optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
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code : #24#4#16;
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flags : if_arm7
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),
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(
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opcode : A_LDR;
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ops : 3;
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optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
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code : #25#4#16;
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flags : if_arm7
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),
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(
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opcode : A_LDR;
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ops : 3;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
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code : #32#6#16;
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flags : if_arm7
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),
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(
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opcode : A_LDR;
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ops : 4;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate or ot_bits32);
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code : #33#6#16;
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flags : if_arm7
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),
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(
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opcode : A_LDRH;
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ops : 2;
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@ -427,6 +406,13 @@
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code : #8#1#160;
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flags : if_arm7
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),
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(
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opcode : A_MOV;
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ops : 2;
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optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none);
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code : #8#1#160;
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flags : if_arm7
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),
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(
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opcode : A_MUL;
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ops : 3;
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@ -619,36 +605,15 @@
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(
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opcode : A_STR;
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ops : 2;
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optypes : (ot_reg32,ot_immediate or ot_bits32,ot_none,ot_none);
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code : #23#5#0;
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optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
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code : #23#4#0;
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flags : if_arm7
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),
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(
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opcode : A_STR;
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opcode : A_STRB;
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ops : 2;
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optypes : (ot_reg32,ot_reg32,ot_none,ot_none);
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code : #24#4#0;
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flags : if_arm7
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),
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(
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opcode : A_STR;
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ops : 3;
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optypes : (ot_reg32,ot_reg32,ot_immediate or ot_bits32,ot_none);
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code : #25#4#0;
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flags : if_arm7
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),
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(
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opcode : A_STR;
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ops : 3;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none);
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code : #32#6#0;
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flags : if_arm7
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),
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(
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opcode : A_STR;
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ops : 4;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_immediate or ot_bits32);
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code : #33#6#0;
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optypes : (ot_reg32,ot_memoryam2,ot_none,ot_none);
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code : #23#6#0;
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flags : if_arm7
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),
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(
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