paweld/fpc
1
0
Fork 0
mirror of https://gitlab.com/freepascal.org/fpc/source.git synced 2025-08-12 19:29:27 +02:00
Code Issues Packages Projects Releases Wiki Activity

* handle also LOC_CREGISTER/LOC_CMMREGISTER in tcgvecnode.pass_generate_code, resolves #24705

Browse Source 
git-svn-id: trunk@25039 -
This commit is contained in:
florian 2013-07-04 19:36:28 +00:00
parent 59d6df4fca
commit 963a488ca2
3 changed files with 29 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitattributes vendored
View File

@ -13454,6 +13454,7 @@ tests/webtbs/tw2438.pp svneol=native#text/plain
tests/webtbs/tw2442.pp svneol=native#text/plain tests/webtbs/tw2442.pp svneol=native#text/plain
tests/webtbs/tw2452.pp svneol=native#text/plain tests/webtbs/tw2452.pp svneol=native#text/plain
tests/webtbs/tw2454.pp svneol=native#text/plain tests/webtbs/tw2454.pp svneol=native#text/plain
tests/webtbs/tw24705.pp svneol=native#text/pascal
tests/webtbs/tw2473.pp svneol=native#text/plain tests/webtbs/tw2473.pp svneol=native#text/plain
tests/webtbs/tw2480.pp svneol=native#text/plain tests/webtbs/tw2480.pp svneol=native#text/plain
tests/webtbs/tw2481.pp svneol=native#text/plain tests/webtbs/tw2481.pp svneol=native#text/plain

2
compiler/ncgmem.pas
View File

@ -921,6 +921,8 @@ implementation
begin begin
{ may happen in case of function results } { may happen in case of function results }
case left.location.loc of case left.location.loc of
LOC_CREGISTER,
LOC_CMMREGISTER,
LOC_REGISTER, LOC_REGISTER,
LOC_MMREGISTER: LOC_MMREGISTER:
hlcg.location_force_mem(current_asmdata.CurrAsmList,left.location,left.resultdef); hlcg.location_force_mem(current_asmdata.CurrAsmList,left.location,left.resultdef);

26
tests/webtbs/tw24705.pp Normal file
View File

@ -0,0 +1,26 @@
{ %OPT=-O2 }
{$ifdef fpc}
{$mode objfpc}
{$endif}
{$apptype console}
type
TTest = record
x: byte;
end;
TByte = array [ 0 .. 0 ] of byte;
function test( dummy: integer ): TTest;
begin
result.x := dummy;
TByte( result.x )[0] := result.x;
end;
begin
if test( $5A ).x = $5A then
writeln( 'pass' )
else
halt( 1 );
end.