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Refactor and secure some immediate operand encodings.
Add some system mode entries, udiv/sdiv in arm mode, and fix bugs in ldrh/strh. git-svn-id: branches/laksen/armiw@29353 -
This commit is contained in:
Jeppe Johansen
parent
e7575d9f96
commit
9a482d5281
@ -113,6 +113,7 @@ uses
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OT_AMMASK = $001f0000;
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{ IT instruction }
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OT_CONDITION = $00200000;
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OT_MODEFLAGS = $00400000;
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OT_MEMORYAM2 = OT_MEMORY or OT_AM2;
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OT_MEMORYAM3 = OT_MEMORY or OT_AM3;
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@ -2188,6 +2189,10 @@ implementation
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begin
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ot:=OT_REGS;
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end;
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top_modeflags:
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begin
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ot:=OT_MODEFLAGS;
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end;
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else
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begin writeln(typ);
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internalerror(200402261); end;
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@ -2863,6 +2868,10 @@ implementation
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case oper[1]^.reg of
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NR_APSR,NR_CPSR:;
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NR_SPSR:
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begin
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bytes:=bytes or (1 shl 22);
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end;
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else
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Message(asmw_e_invalid_opcode_and_operands);
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end;
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@ -2877,13 +2886,22 @@ implementation
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if oper[0]^.typ=top_specialreg then
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begin
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if oper[0]^.specialreg<>NR_CPSR then
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Message1(asmw_e_invalid_opcode_and_operands, 'Can only use CPSR in this form');
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if (oper[0]^.specialreg<>NR_CPSR) and
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(oper[0]^.specialreg<>NR_SPSR) then
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Message1(asmw_e_invalid_opcode_and_operands, '"Invalid special reg"');
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if srF in oper[0]^.specialflags then
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bytes:=bytes or (2 shl 18);
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if srC in oper[0]^.specialflags then
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bytes:=bytes or (1 shl 16);
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if srX in oper[0]^.specialflags then
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bytes:=bytes or (1 shl 17);
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if srS in oper[0]^.specialflags then
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bytes:=bytes or (1 shl 18);
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if srF in oper[0]^.specialflags then
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bytes:=bytes or (1 shl 19);
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{ Set R bit }
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if oper[0]^.specialreg=NR_SPSR then
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bytes:=bytes or (1 shl 22);
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end
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else
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case oper[0]^.reg of
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@ -3002,16 +3020,11 @@ implementation
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offset:=currsym.offset-insoffset-8;
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offset:=offset+oper[1]^.ref^.offset;
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if offset>=0 then
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begin
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{ set U flag }
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bytes:=bytes or (1 shl 23);
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bytes:=bytes or offset
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end
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{ set U flag }
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bytes:=bytes or (1 shl 23)
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else
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begin
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offset:=-offset;
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bytes:=bytes or offset
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end;
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offset:=-offset;
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bytes:=bytes or (offset and $FFF);
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end
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else
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begin
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@ -3090,18 +3103,12 @@ implementation
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offset:=currsym.offset-insoffset-8;
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offset:=offset+refoper^.ref^.offset;
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if offset>=0 then
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begin
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{ set U flag }
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bytes:=bytes or (1 shl 23);
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bytes:=bytes or (offset and $F);
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bytes:=bytes or ((offset and $F0) shl 4);
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end
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{ set U flag }
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bytes:=bytes or (1 shl 23)
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else
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begin
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offset:=-offset;
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bytes:=bytes or (offset and $F);
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bytes:=bytes or ((offset and $F0) shl 4);
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end;
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offset:=-offset;
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bytes:=bytes or (offset and $F);
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bytes:=bytes or ((offset and $F0) shl 4);
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end
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else
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begin
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@ -3197,19 +3204,14 @@ implementation
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if assigned(currsym) then
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offset:=currsym.offset-insoffset-8;
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offset:=offset+refoper^.ref^.offset;
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if offset>=0 then
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begin
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{ set U flag }
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bytes:=bytes or (1 shl 23);
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bytes:=bytes or (offset and $F);
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bytes:=bytes or ((offset and $F0) shl 4);
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end
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{ set U flag }
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bytes:=bytes or (1 shl 23)
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else
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begin
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offset:=-offset;
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bytes:=bytes or (offset and $F);
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bytes:=bytes or ((offset and $F0) shl 4);
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end;
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offset:=-offset;
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bytes:=bytes or (offset and $F);
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bytes:=bytes or ((offset and $F0) shl 4);
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end
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else
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begin
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@ -3231,18 +3233,14 @@ implementation
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if getregtype(oper[1]^.ref^.index)=R_INVALIDREGISTER then
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begin
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bytes:=bytes or (1 shl 22); // with immediate offset
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if oper[1]^.ref^.offset < 0 then
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begin
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bytes:=bytes or ((-oper[1]^.ref^.offset) and $f0 shl 4);
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bytes:=bytes or ((-oper[1]^.ref^.offset) and $f);
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end
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offset:=oper[1]^.ref^.offset;
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if offset>=0 then
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{ set U flag }
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bytes:=bytes or (1 shl 23)
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else
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begin
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{ set U bit }
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bytes:=bytes or (1 shl 23);
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bytes:=bytes or (oper[1]^.ref^.offset and $f0 shl 4);
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bytes:=bytes or (oper[1]^.ref^.offset and $f);
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end;
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offset:=-offset;
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bytes:=bytes or (offset and $F);
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bytes:=bytes or ((offset and $F0) shl 4);
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end
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else
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begin
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@ -375,9 +375,9 @@ reg32,immshifter \xB\x1\xA0 ARM32,ARMv4
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reg32,regf \x10\x01\x0F ARM32,ARMv4
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[MSRcc]
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regf,reg32 \x12\x01\x28\xF0 ARM32,ARMv4
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regf,immshifter \x13\x03\x28\xF0 ARM32,ARMv4
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regs,immshifter \x13\x03\x28\xF0 ARM32,ARMv4
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regf,reg32 \x12\x01\x20\xF0 ARM32,ARMv4
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regf,immshifter \x13\x03\x20\xF0 ARM32,ARMv4
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regs,immshifter \x13\x03\x20\xF0 ARM32,ARMv4
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[MULcc]
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reglo,reglo \x64\x43\x40 THUMB,ARMv4T
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@ -647,8 +647,12 @@ reg32,reg32,reg32,reg32 \x16\x01\x40\xA ARM32,ARMv5TE
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reg32,reg32,reg32,reg32 \x16\x01\x40\xE ARM32,ARMv5TE
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[SMLAWBcc]
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reg32,reg32,reg32,reg32 \x80\xFB\x30\x0\x00 THUMB32,ARMv6T2
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reg32,reg32,reg32,reg32 \x15\x1\x20\x8 ARM32,ARMv5TE
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[SMLAWTcc]
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reg32,reg32,reg32,reg32 \x80\xFB\x30\x0\x10 THUMB32,ARMv6T2
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reg32,reg32,reg32,reg32 \x15\x1\x20\xC ARM32,ARMv5TE
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[VLDMcc]
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memam4,reglist \x44\xC\x10\xA ARM32,VFPv2
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@ -1331,9 +1335,11 @@ reglist \x26\x80 ARM32,ARMv4
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[SDIVcc]
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reg32,reg32,reg32 \x80\xFB\x90\xF0\xF0 THUMB32,ARMv7R,ARMv7M
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reg32,reg32,reg32 \x15\x07\x10\x01\xF ARM32,ARMv7
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[UDIVcc]
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reg32,reg32,reg32 \x80\xFB\xB0\xF0\xF0 THUMB32,ARMv7R,ARMv7M
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reg32,reg32,reg32 \x15\x07\x30\x01\xF ARM32,ARMv7
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[MOVTcc]
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reg32,imm \x81\xF2\xC0\x0\x0 THUMB32,ARMv6T2
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@ -1501,6 +1507,7 @@ immshifter \x2E\xF5\x7F\xF0\x40 ARM32,ARMv7
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[SMC]
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immshifter \x2E\x01\x60\x00\x70 ARM32,ARMv7
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imm32 \x2E\x01\x60\x00\x70 ARM32,ARMv7
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; Thumb armv6-m (gcc)
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[NEG]
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@ -1,2 +1,2 @@
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{ don't edit, this file is generated from armins.dat }
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703;
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710;
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@ -1187,21 +1187,21 @@
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opcode : A_MSR;
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ops : 2;
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optypes : (ot_regf,ot_reg32,ot_none,ot_none,ot_none,ot_none);
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code : #18#1#40#240;
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code : #18#1#32#240;
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flags : if_arm32 or if_armv4
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),
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(
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opcode : A_MSR;
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ops : 2;
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optypes : (ot_regf,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
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code : #19#3#40#240;
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code : #19#3#32#240;
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flags : if_arm32 or if_armv4
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),
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(
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opcode : A_MSR;
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ops : 2;
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optypes : (ot_regs,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
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code : #19#3#40#240;
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code : #19#3#32#240;
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flags : if_arm32 or if_armv4
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),
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(
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@ -2310,6 +2310,34 @@
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code : #22#1#64#14;
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flags : if_arm32 or if_armv5te
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),
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(
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opcode : A_SMLAWB;
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ops : 4;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
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code : #128#251#48#0#0;
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flags : if_thumb32 or if_armv6t2
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),
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(
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opcode : A_SMLAWB;
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ops : 4;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
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code : #21#1#32#8;
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flags : if_arm32 or if_armv5te
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),
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(
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opcode : A_SMLAWT;
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ops : 4;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
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code : #128#251#48#0#16;
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flags : if_thumb32 or if_armv6t2
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),
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(
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opcode : A_SMLAWT;
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ops : 4;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none);
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code : #21#1#32#12;
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flags : if_arm32 or if_armv5te
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),
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(
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opcode : A_VLDM;
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ops : 2;
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@ -4354,6 +4382,13 @@
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code : #128#251#144#240#240;
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flags : if_thumb32 or if_armv7r or if_armv7m
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),
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(
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opcode : A_SDIV;
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ops : 3;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
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code : #21#7#16#1#15;
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flags : if_arm32 or if_armv7
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),
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(
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opcode : A_UDIV;
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ops : 3;
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@ -4361,6 +4396,13 @@
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code : #128#251#176#240#240;
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flags : if_thumb32 or if_armv7r or if_armv7m
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),
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(
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opcode : A_UDIV;
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ops : 3;
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optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
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code : #21#7#48#1#15;
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flags : if_arm32 or if_armv7
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),
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(
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opcode : A_MOVT;
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ops : 2;
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@ -4872,6 +4914,13 @@
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code : #46#1#96#0#112;
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flags : if_arm32 or if_armv7
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),
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(
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opcode : A_SMC;
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ops : 1;
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optypes : (ot_immediate or ot_bits32,ot_none,ot_none,ot_none,ot_none,ot_none);
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code : #46#1#96#0#112;
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flags : if_arm32 or if_armv7
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),
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(
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opcode : A_SVC;
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ops : 1;
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@ -1190,6 +1190,7 @@ Unit raarmgas;
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((operandnum=3) and not(instr.opcode in [A_UMLAL,A_UMULL,A_SMLAL,A_SMULL,A_MLA,A_UMAAL,A_MLS,
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A_SMLABB,A_SMLABT,A_SMLATB,A_SMLATT,A_SMMLA,A_SMMLS,A_SMLAD,A_SMLALD,A_SMLSD,
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A_SMLALBB,A_SMLALBT,A_SMLALTB,A_SMLALTT,A_SMLSLD,
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A_SMLAWB,A_SMLAWT,
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A_MRC,A_MCR,A_MCRR,A_MRRC,A_MRC2,A_MCR2,A_MCRR2,A_MRRC2,
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A_STREXD,A_STRD,
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A_USADA8,
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