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* started to get some Z80 things working
git-svn-id: branches/z80@44284 -
This commit is contained in:
florian
parent
1e3901c298
commit
9a4ff8daa4
@ -297,6 +297,7 @@ unit cgobj;
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procedure a_op_ref_reg(list : TAsmList; Op: TOpCG; size: TCGSize; const ref: TReference; reg: TRegister); virtual;
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procedure a_op_reg_loc(list : TAsmList; Op: TOpCG; reg: tregister; const loc: tlocation);
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procedure a_op_ref_loc(list : TAsmList; Op: TOpCG; const ref: TReference; const loc: tlocation);
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procedure a_op_loc_reg(list : TAsmList; Op: TOpCG; const loc: tlocation; reg: tregister);
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{ trinary operations for processors that support them, 'emulated' }
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{ on others. None with "ref" arguments since I don't think there }
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@ -640,7 +641,8 @@ implementation
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end;
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function Tcg.makeregsize(list:TAsmList;reg:Tregister;size:Tcgsize):Tregister;
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function tcg.makeregsize(list : TAsmList; reg : Tregister; size : Tcgsize
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) : Tregister;
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var
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subreg:Tsubregister;
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begin
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@ -1741,10 +1743,8 @@ implementation
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procedure tcg.a_op_ref_loc(list : TAsmList; Op: TOpCG; const ref: TReference; const loc: tlocation);
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var
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tmpreg: tregister;
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begin
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case loc.loc of
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LOC_REGISTER,LOC_CREGISTER:
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@ -1761,8 +1761,22 @@ implementation
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end;
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procedure Tcg.a_op_const_reg_reg(list:TAsmList;op:Topcg;size:Tcgsize;
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a:tcgint;src,dst:Tregister);
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procedure tcg.a_op_loc_reg(list : TAsmList; Op : TOpCG;
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const loc : tlocation; reg : tregister);
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begin
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case loc.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_op_reg_reg(list,op,loc.size,loc.register,reg);
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LOC_REFERENCE,LOC_CREFERENCE:
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a_op_ref_reg(list,op,loc.size,loc.reference,reg);
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else
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internalerror(2019020903);
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end;
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end;
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procedure tcg.a_op_const_reg_reg(list : TAsmList; op : TOpCg;
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size : tcgsize; a : tcgint; src,dst : tregister);
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begin
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optimize_op_const(size, op, a);
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case op of
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@ -2095,7 +2109,8 @@ implementation
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end;
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procedure tcg.a_loadmm_intreg_reg(list: tasmlist; fromsize,tosize: tcgsize; intreg,mmreg: tregister; shuffle: pmmshuffle);
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procedure tcg.a_loadmm_intreg_reg(list : TAsmList; fromsize,
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tosize : tcgsize; intreg,mmreg : tregister; shuffle : pmmshuffle);
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var
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tmpref: treference;
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begin
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@ -2109,7 +2124,8 @@ implementation
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end;
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procedure tcg.a_loadmm_reg_intreg(list: tasmlist; fromsize,tosize: tcgsize; mmreg,intreg: tregister; shuffle: pmmshuffle);
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procedure tcg.a_loadmm_reg_intreg(list : TAsmList; fromsize,
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tosize : tcgsize; mmreg,intreg : tregister; shuffle : pmmshuffle);
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var
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tmpref: treference;
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begin
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@ -2477,7 +2493,8 @@ implementation
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end;
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procedure tcg.a_mul_reg_reg_pair(list: TAsmList; size: TCgSize; src1,src2,dstlo,dsthi: TRegister);
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procedure tcg.a_mul_reg_reg_pair(list : TAsmList; size : tcgsize; src1,src2,
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dstlo,dsthi : TRegister);
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begin
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internalerror(2014060801);
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end;
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@ -112,6 +112,8 @@ unit cgcpu;
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procedure a_op64_const_reg(list : TAsmList;op:TOpCG;size : tcgsize;value : int64;reg : tregister64);override;
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end;
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function GetByteLoc(const loc : tlocation;nr : byte) : tlocation;
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procedure create_codegen;
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const
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@ -2187,6 +2189,34 @@ unit cgcpu;
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end;
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function GetByteLoc(const loc : tlocation; nr : byte) : tlocation;
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var
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i : Integer;
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begin
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Result:=loc;
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Result.size:=OS_8;
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case loc.loc of
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LOC_REFERENCE,LOC_CREFERENCE:
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inc(Result.reference.offset,nr);
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LOC_REGISTER,LOC_CREGISTER:
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begin
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if nr>=4 then
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Result.register:=Result.register64.reghi;
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nr:=nr mod 4;
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for i:=1 to nr do
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Result.register:=GetNextReg(Result.register);
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end;
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LOC_CONSTANT:
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if loc.size in [OS_64,OS_S64] then
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Result.value:=(Result.value64 shr (nr*8)) and $ff
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else
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Result.value:=(Result.value shr (nr*8)) and $ff;
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else
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Internalerror(2019020902);
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end;
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end;
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procedure create_codegen;
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begin
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cg:=tcgz80.create;
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@ -204,7 +204,8 @@ unit cpupara;
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begin
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{ In case of po_delphi_nested_cc, the parent frame pointer
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is always passed on the stack. }
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if (nextintreg<>RS_HL) and
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if false and { no fastcall yet }
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(nextintreg=RS_HL) and
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(not(vo_is_parentfp in hp.varoptions) or
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not(po_delphi_nested_cc in p.procoptions)) then
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begin
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@ -345,7 +346,7 @@ unit cpupara;
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inc(nextintreg);
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end
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else
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{ parameters are always passed completely in registers or in memory on avr }
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{ parameters are always passed completely in registers or in memory on Z80 }
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internalerror(2015041002);
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dec(paralen,tcgsize2size[paraloc^.size]);
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end;
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@ -365,7 +366,7 @@ unit cpupara;
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paraloc^.reference.offset:=stack_offset;
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inc(stack_offset,hp.vardef.size);
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end;
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dec(paralen,hp.vardef.size);
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paralen:=0;
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end;
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else
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internalerror(2002071002);
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@ -187,35 +187,15 @@ interface
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tmpreg1,tmpreg2 : tregister;
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i : longint;
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begin
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//pass_left_right;
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//force_reg_left_right(true,true);
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//
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//unsigned:=not(is_signed(left.resultdef)) or
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// not(is_signed(right.resultdef));
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//
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//if getresflags(unsigned)=F_NotPossible then
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// begin
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// swapleftright;
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// { if we have to swap back and left is a constant, force it to a register because we cannot generate
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// the needed code using a constant }
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// if (left.location.loc=LOC_CONSTANT) and (left.location.value<>0) then
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// hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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// end;
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//
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//if right.location.loc=LOC_CONSTANT then
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// begin
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// { decrease register pressure on registers >= r16 }
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// if (right.location.value and $ff)=0 then
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// current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CP,left.location.register,NR_R1))
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// else
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// current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CPI,left.location.register,right.location.value and $ff))
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// end
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//{ on the left side, we allow only a constant if it is 0 }
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//else if (left.location.loc=LOC_CONSTANT) and (left.location.value=0) then
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// current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CP,NR_R1,right.location.register))
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//else
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// current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CP,left.location.register,right.location.register));
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//
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pass_left_right;
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// force_reg_left_right(true,true);
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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cg.a_load_loc_reg(current_asmdata.CurrAsmList,OS_8,GetByteLoc(left.location,0),NR_A);
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cg.a_op_loc_reg(current_asmdata.CurrAsmList,OP_SUB,GetByteLoc(right.location,0),NR_A);
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//tmpreg1:=left.location.register;
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//tmpreg2:=right.location.register;
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//
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