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+ z80: add operand info to the result of taicpu.GetString, this makes the

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compiler produce nicer error messages, when it encounters an invalid
  instruction in inline asm code

git-svn-id: trunk@45187 -
This commit is contained in:
nickysn 2020-04-30 00:17:29 +00:00
parent 2f4390ac9b
commit 9b1eebd333
1 changed files with 69 additions and 115 deletions
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184
compiler/z80/aasmcpu.pas
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@ -566,124 +566,78 @@ implementation
function taicpu.GetString: string; function taicpu.GetString: string;
var var
//i : longint; i : longint;
s : string; s : string;
//regnr: string; first: Boolean;
//addsize : boolean;
begin begin
s:='['+std_op2str[opcode]; s:='['+std_op2str[opcode];
//for i:=0 to ops-1 do for i:=0 to ops-1 do
// begin begin
// with oper[i]^ do with oper[i]^ do
// begin begin
// if i=0 then if i=0 then
// s:=s+' ' begin
// else s:=s+' ';
// s:=s+','; if condition<>C_None then
// { type } s:=s+cond2str[condition]+',';
// addsize:=false; end
// else
// regnr := ''; s:=s+',';
// if getregtype(reg) = R_MMREGISTER then case typ of
// str(getsupreg(reg),regnr); top_reg:
// s:=s+std_regname(reg);
// if (ot and OT_XMMREG)=OT_XMMREG then top_const:
// s:=s+'xmmreg' + regnr s:=s+'const';
// else top_ref:
// if (ot and OT_YMMREG)=OT_YMMREG then case ref^.refaddr of
// s:=s+'ymmreg' + regnr addr_full:
// else s:=s+'addr16';
// if (ot and OT_ZMMREG)=OT_ZMMREG then addr_lo8:
// s:=s+'zmmreg' + regnr s:=s+'addr_lo8';
// addr_hi8:
// else s:=s+'addr_hi8';
// if (ot and OT_REG_EXTRA_MASK)=OT_MMXREG then addr_no:
// s:=s+'mmxreg' begin
// else s:=s+'(';
// if (ot and OT_REG_EXTRA_MASK)=OT_FPUREG then first:=true;
// s:=s+'fpureg' if ref^.base<>NR_NO then
// else begin
// if (ot and OT_REGISTER)=OT_REGISTER then first:=false;
// begin s:=s+std_regname(ref^.base);
// s:=s+'reg'; end;
// addsize:=true; if ref^.index<>NR_NO then
// end begin
// else if not first then
// if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then s:=s+'+';
// begin first:=false;
// s:=s+'imm'; s:=s+std_regname(ref^.index);
// addsize:=true; end;
// end if assigned(ref^.symbol) then
// else begin
// if (ot and OT_MEMORY)=OT_MEMORY then if not first then
// begin s:=s+'+';
// s:=s+'mem'; first:=false;
// addsize:=true; s:=s+'addr16';
// end end;
// else if ref^.offset<>0 then
// s:=s+'???'; begin
// { size } if not first then
// if addsize then s:=s+'+';
// begin if (ref^.offset>=-128) and (ref^.offset<=127) then
// if (ot and OT_BITS8)<>0 then s:=s+'const8'
// s:=s+'8' else
// else s:=s+'const16';
// if (ot and OT_BITS16)<>0 then end;
// s:=s+'16' s:=s+')';
// else end;
// if (ot and OT_BITS32)<>0 then else
// s:=s+'32' ;
// else end;
// if (ot and OT_BITS64)<>0 then else
// s:=s+'64' ;
// else end;
// if (ot and OT_BITS128)<>0 then end;
// s:=s+'128' end;
// else
// if (ot and OT_BITS256)<>0 then
// s:=s+'256'
// else
// if (ot and OT_BITS512)<>0 then
// s:=s+'512'
// else
// s:=s+'??';
// { signed }
// if (ot and OT_SIGNED)<>0 then
// s:=s+'s';
// end;
//
// if vopext <> 0 then
// begin
// str(vopext and $07, regnr);
// if vopext and OTVE_VECTOR_WRITEMASK = OTVE_VECTOR_WRITEMASK then
// s := s + ' {k' + regnr + '}';
//
// if vopext and OTVE_VECTOR_ZERO = OTVE_VECTOR_ZERO then
// s := s + ' {z}';
//
// if vopext and OTVE_VECTOR_SAE = OTVE_VECTOR_SAE then
// s := s + ' {sae}';
//
//
// if vopext and OTVE_VECTOR_BCST = OTVE_VECTOR_BCST then
// case vopext and OTVE_VECTOR_BCST_MASK of
// OTVE_VECTOR_BCST2: s := s + ' {1to2}';
// OTVE_VECTOR_BCST4: s := s + ' {1to4}';
// OTVE_VECTOR_BCST8: s := s + ' {1to8}';
// OTVE_VECTOR_BCST16: s := s + ' {1to16}';
// end;
//
// if vopext and OTVE_VECTOR_ER = OTVE_VECTOR_ER then
// case vopext and OTVE_VECTOR_ER_MASK of
// OTVE_VECTOR_RNSAE: s := s + ' {rn-sae}';
// OTVE_VECTOR_RDSAE: s := s + ' {rd-sae}';
// OTVE_VECTOR_RUSAE: s := s + ' {ru-sae}';
// OTVE_VECTOR_RZSAE: s := s + ' {rz-sae}';
// end;
//
// end;
// end;
// end;
GetString:=s+']'; GetString:=s+']';
end; end;