From 9c461d90bd534b4bcae18cf94c642bd5567e86b6 Mon Sep 17 00:00:00 2001
From: nickysn <nickysn@gmail.com>
Date: Wed, 22 Apr 2020 22:37:20 +0000
Subject: [PATCH] + handle ref.base=NR_HL/NR_BC/NR_SP in
 tcgz80.a_loadaddr_ref_reg

git-svn-id: branches/z80@45009 -
---
 compiler/z80/cgcpu.pas | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/compiler/z80/cgcpu.pas b/compiler/z80/cgcpu.pas
index 572a838824..875ea895e4 100644
--- a/compiler/z80/cgcpu.pas
+++ b/compiler/z80/cgcpu.pas
@@ -2195,6 +2195,19 @@ unit cgcpu;
             if ref.offset<>0 then
               a_op_const_reg(list,OP_ADD,OS_16,ref.offset,r);
           end
+        else if (ref.base=NR_SP) or (ref.base=NR_BC) or (ref.base=NR_DE) then
+          begin
+            getcpuregister(list,NR_H);
+            getcpuregister(list,NR_L);
+            list.Concat(taicpu.op_reg_const(A_LD,NR_HL,ref.offset));
+            list.Concat(taicpu.op_reg_reg(A_ADD,NR_HL,ref.base));
+            emit_mov(list,r,NR_L);
+            ungetcpuregister(list,NR_L);
+            emit_mov(list,GetNextReg(r),NR_H);
+            ungetcpuregister(list,NR_H);
+            if (ref.index<>NR_NO) then
+              a_op_reg_reg(list,OP_ADD,OS_16,ref.index,r);
+          end
         else
           begin
             a_load_const_reg(list,OS_16,ref.offset,r);