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* fix spilling of avx(512) registers

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* get_scalar_mm_op fixed for M256

git-svn-id: trunk@47524 -
This commit is contained in:
florian 2020-11-21 22:30:34 +00:00
parent 1d474f822e
commit 9c7cb3dbd7
2 changed files with 26 additions and 1 deletions
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20
compiler/x86/aasmcpu.pas
View File

@ -4784,6 +4784,16 @@ implementation
R_SUBQ,
R_SUBMMWHOLE:
result:=taicpu.op_ref_reg(A_VMOVQ,S_NO,tmpref,r);
R_SUBMMY:
if ref.alignment>=32 then
result:=taicpu.op_ref_reg(A_VMOVDQA,S_NO,tmpref,r)
else
result:=taicpu.op_ref_reg(A_VMOVDQU,S_NO,tmpref,r);
R_SUBMMZ:
if ref.alignment>=64 then
result:=taicpu.op_ref_reg(A_VMOVDQA64,S_NO,tmpref,r)
else
result:=taicpu.op_ref_reg(A_VMOVDQU64,S_NO,tmpref,r);
R_SUBMMX:
result:=taicpu.op_ref_reg(A_VMOVDQU,S_NO,tmpref,r);
else
@ -4843,6 +4853,16 @@ implementation
result:=taicpu.op_reg_ref(A_VMOVSD,S_NO,r,tmpref);
R_SUBMMS:
result:=taicpu.op_reg_ref(A_VMOVSS,S_NO,r,tmpref);
R_SUBMMY:
if ref.alignment>=32 then
result:=taicpu.op_reg_ref(A_VMOVDQA,S_NO,r,tmpref)
else
result:=taicpu.op_reg_ref(A_VMOVDQU,S_NO,r,tmpref);
R_SUBMMZ:
if ref.alignment>=64 then
result:=taicpu.op_reg_ref(A_VMOVDQA64,S_NO,r,tmpref)
else
result:=taicpu.op_reg_ref(A_VMOVDQU64,S_NO,r,tmpref);
R_SUBQ,
R_SUBMMWHOLE:
result:=taicpu.op_reg_ref(A_VMOVQ,S_NO,r,tmpref);

7
compiler/x86/cgx86.pas
View File

@ -1399,7 +1399,12 @@ unit cgx86;
OS_M512:
{ 256-bit aligned vector }
if UseAVX then
result:=A_VMOVAPS
begin
if aligned then
result:=A_VMOVAPS
else
result:=A_VMOVUPS;
end
else
{ SSE does not support 256-bit or 512-bit vectors }
InternalError(2018012930);